Abstract: An antenna includes a substantially planer substrate and a helical winding. The substantially planer substrate includes a first surface and a second surface. The helical winding includes a first pattern, a second pattern, and a plurality of interconnections. The first pattern is affixed to the first surface and the second pattern is affixed to the second surface. Connection nodes of the first pattern are coupled to associated connection nodes of the second pattern by the plurality of interconnections.

Abstract: A method and apparatus for providing improved security and improved roaming transition times in wireless networks. In the present invention, the same pairwise master key (PMK) from an authentication server can be used across multiple access points and a new pairwise transition key (PTK) is derived for each association of a station to any of the access points. A plurality of access points are organized in functional hierarchical levels and are operable to advertise an indicator of the PMK cache depth supported by a group of access points (N) and an ordered list of the identifiers for the derivation path. Access points in each level in the cache hierarchy compute the derived pairwise master keys (DPMKs) for devices in the next lower level in the hierarchy and then deliver the DPMKs to those devices. An access point calculates the PTK as part of the security exchange process when the station wishes to associate to the access point. The station also computes the PTK as part of the security exchange process.

Abstract: Certain embodiments of the invention may be found in a method and system for antenna selection diversity with prediction. An antenna diversity system may use information that it has stored on the antenna selection process in previous frames to predict the starting receiving antenna and the starting transmission antenna for the next frame. The prediction may be based on which antennas were selected in previous frames or may be based metrics associated with performance of the antennas. Prediction may be based on a majority polling scheme of previously selected antennas in a determined number of previous frames. Prediction may also be based on a weighted sum of at least one selection metric for all antennas in a determined number of previous frames. Antenna prediction provides a significant performance improvement by reducing the processing and operational overhead in cases where a transmit or a receive antenna dominates.

Abstract: Sample rate reduction in data communication receivers. Digital sampling of analog data is performed using a reduced sample rate. The reduction factor may be any number of factors including a factor that divides the sample rate by a factor of two. The reduction of the sampling frequency is from a sampling frequency that is greater than twice the highest frequency component in an analog input signal. These analog input signals may be I and Q streams in certain embodiments. A digital interpolation filter may be employed to increase (up-convert) the sample rate of a digital signal before it is input to a VID filter that is used to recover the transmitted symbols from the over-sampled data stream. In this embodiment, this technique allows a front end of a communication receiver to be clocked at a lower sampling rate without affecting the performance of the VID filter.

Abstract: An apparatus and a method for routing data in a radio data communication system having one or more host computers, one or more intermediate base stations, and one or more RF terminals organizes the intermediate base stations into an optimal spanning-tree network to control the routing of data to and from the RF terminals and the host computer efficiently and dynamically. Communication between the host computer and the RF terminals is achieved by using the network of intermediate base stations to transmit the data.

Abstract: A method and system for copying operating system information to said at least two storage devices, selectively hiding at least one, but not all, of the storage devices from being accessed by the operating system, and selectively revealing one or more of said hidden storage devices as needed to permit access to the information stored therein.

Abstract: A first set of instructions associated with an egress of a datagram may be determined, the first set of instructions identifying a first subset of a second set of instructions, the first subset including multiple individual network identifiers identifying which network portion to transmit a replication of the datagram. Which one of the multiple individual network identifiers corresponds to the datagram may be determined from the first subset of the second set of instructions and may be based on the egress of the datagram, wherein each network identifier corresponds to a different egress. The replication of the datagram may be provided to the egress of the determined network identifier for transmission to the network portion as identified by the determined network identifier corresponding to the datagram.

Abstract: A frequency translation module for a broadband multi-channel communication system may include an analog signal converter, a digital channel selection device, and a digital-to-analog (D/A) converter. The analog signal converter is configured to receive a plurality of analog signals, to select analog signals residing in a predefined frequency band, and to convert each of the selected analog signals into a digital signal. The digital channel selection device is configured to process digital signals corresponding to the selected analog signals and to generate a composite output of digital signals representative of the selected analog signals. The D/A converter is configured to translate the composite output to an analog signal output decodable by a receiver. Further, the frequency translation module may include a mixer configured to upconvert the analog signal output to a frequency decodable by the receiver.

Abstract: Methods and systems for a low noise amplifier with tolerance to large inputs are disclosed. Aspects of one method may include providing an individual current source for each input transistor to a low noise amplifier (LNA), wherein the individual current sources may be isolated from each other when the LNA is turned off. The individual current sources may also form a common current source for the input transistors when the LNA is turned on. Accordingly, the input transistors to the LNA may float when the LNA is turned off, thereby coupling the input signal voltage to the source and drain terminals. The individual current sources may be isolated from each other by a coupling transistor that is turned off. When the LNA is turned on, the coupling transistor may be turned on to couple the individual current sources to each other to form the common current source for the input transistors.

Abstract: Systems and methods for generation of time-dependent control signals for video signals are provided. A system is provided that includes a set of microsequencers, a programmable combinational logic (PCL) module, shared memory, an arbiter for sharing of memory by the microsequencers, stacks containing registers for microsequencer control, and a control interface. The system can efficiently provide control signals for video signals, implement the MACROVISION copy protection process, and provide other value added features. The method includes accessing programs from shared memory, such that a set of microsequencers can generate flags. These flags are then processed to generate one or more control signals used to support the outputting of video signals including those requiring MACROVISION copy protection.

Abstract: An unconditionally stable on-chip filter includes a filtering section and at least one negative resistance module. The filtering section is operably coupled to filter a signal and includes realizable integrated circuit passive components. The at least one negative resistance module is operably coupled to compensate for integrated circuit losses of the filtering section. The realizable integrated circuit passive components have values that are robust, in comparison to parasitic values, have minimal integrated circuit real estate, and provide realizable values for various integrated circuit manufacturing processes including CMOS technology.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video.

Abstract: A network device for processing packets. The network device includes applying specific fields from a packet to an associated memory device and comparing means for comparing input to the memory device with entries in the memory device. The network device also includes enabling means for enabling selection of bits, by the memory device, that are required to match exactly with bits from the input to the memory device. The network device further includes outputting means for outputting an address for a matched entry by the memory device and applying means for applying a match from the memory device to an associated entry in a table for applying actions from the table that are associated with the match to the packet.

Abstract: Herein described is a method and system of prioritizing access to data stored in one or more data processing devices communicatively coupled to the data storage device. The method may be based on the type of data file accessed. Prioritization may be based on data pool or share names. Further, one or more data ports of the data storage device may be used to prioritize access to one or more data files stored in the data storage device. The system may comprise a storage device, one or more data processing devices requesting data file access from the data storage device, a software resident in a memory of the data storage device, a processor executing the software, and a display.

Abstract: Method and apparatus for processing location service messages in a satellite position location system is described. In one example, a mobile receiver includes a satellite signal receiver, wireless circuitry, and at least one module. The satellite signal receiver is configured to receive satellite positioning system signals, such as Global Positioning System (GPS) signals. The wireless circuitry is configured to communicate location service messages between the mobile receiver and a server through a cellular communication network. The location service messages may include any type of data related to A-GPS operation, such as assistance data, position data, request and response data, and the like. The at least one module is configured to provide a user-plane interface and a control-plane interface between the satellite signal receiver and the wireless transceiver.

Abstract: A radio frequency transmitter includes a baseband transmit processing module, a mixing module, a power amplifier, a transmit power sense module, and a transmit power control module. The baseband transmit processing module is operably coupled to encode outbound data into outbound baseband signals in accordance with one of a plurality of encoding protocols. The mixing module is operably coupled to convert the outbound baseband signals into outbound radio frequency signals. The power amplifier is operably coupled to amplify the outbound RF signals prior to transmission to produce amplified outbound RF signals. The transmit power sense module is operably coupled to sense the amplified outbound RF signals to provide a transmit signal strength indication (TSSI). The transmit power control module is operably coupled to adjust gain of the baseband transmit processing module, the mixing module, and/or the power amplifier based on the TSSI and the particular encoding protocol used to produce the baseband signals.

Abstract: A method and apparatus are provided for enabling a transmitter to have a substantially linear magnitude response and a substantially linear phase response. The transmitter includes first and second programmable gain amplifiers (PGAs). The first PGA is tuned to have a resonant frequency that is less than an operating frequency of the first PGA. The second PGA is tuned to have a resonant frequency that is greater than an operating frequency of the second PGA. A magnitude response at an output of the first PGA and a magnitude response at an output of the second PGA combine to provide a substantially linear magnitude response across a frequency range that includes the operating frequency of the first or second PGA. According to an embodiment, the first and second PGAs have the same operating frequency.

Abstract: A SIMD processor includes an ALU having data interconnects facilitating the concurrent processing of overlapping data portions of at least one operand store. Such interconnects facilitate the calculation of shift-invariant convolutions, and sum of absolute differences between an operand in the operand store and another operand.

Abstract: Methods and apparatus are provided for implementing a cryptography engine for cryptography processing. A variety of techniques are described. A cryptography engine such as a DES engine running at a clock frequency higher than that of surrounding logic can be synchronized with the surrounding logic using a frequency synchronizer. Sbox logic output can be more efficiently determined by intelligently arranging Sbox input.

Abstract: Timing vectors are used to pass execution of time-dependent operations from firmware/software to a hardware component (e.g., a state machine). These vectors may be stored as a vector table in a data memory that is accessible by both the firmware/software and the hardware component. Based on the processing being performed in the system, the firmware/software will determine that one or more operations are to be performed at a certain time. The firmware/software stores a reference to that time and the operation(s) in a vector. The hardware component monitors time in the system and the vectors to determine whether the current time matches the time associated with a given vector. When there is a match, the hardware component causes the operation(s) associated with the vector to be performed. The system also may perform different operations at a given time depending on the operating condition (e.g., state) of the system.