Abstract: A self-biasing slicer includes a self-biased differential transistor pair. As a result of the self-biasing, the slicer may receive input signals without the use of AC coupling. That is, a differential input signal may be fed directly to the inputs of the differential transistor pair. The differential pair circuit may incorporate a self-biased load and a self-biased current source. The slicer also may include a matched output stage with inverters that provide a rail-to-rail output. Here, the inverters may incorporate components that are matched with components of the differential pair.

Abstract: Methods and apparatus are provided for decoupling a cryptography accelerator interface from cryptographic processing cores. A shared resource is provided at the cryptography accelerator interface having multiple input ports. References to data in the shared resource are provided to allow processing and ordering of data in preparation for processing by cryptographic processing cores without substantial numbers of separate buffers in the cryptographic processing data paths.

Abstract: Multiple access hard disk. Multiple read-write heads are implemented within a single information storage device. The information storage device can be any of a variety of information storage devices including a hard disk drive (HDD), a CD-ROM (Compact Disc Read Only Memory) drive, a DVD (Digital Video Disc or Digital Versatile Disc) drive, a read-write capable CD (Compact Disc) drive, or a read-write capable DVD drive. Each read-write head may couple to a separate user (or separate device, and/or separate network). Alternatively, more than one of the read-write heads may couple to a single user (or single device, and/or single network). The manner in which each of these read-write heads may be implemented within the information storage device can be varied. If desired, the read-write heads can be arranged in a spoke-like arrangement around a circumference of a circular, spin-capable storage media.

Abstract: A system and method for reducing power consumption during periods of low link utilization. A single enhanced core can be defined that enables operation of subset of parent physical layer devices (PHYs). The subset and parent PHYs can have a fundamental relationship that enables synchronous switching between them depending on the link utilization state.

Abstract: Systems and methods for improving HDCP (High-Bandwidth Digital Content Protection) authentication with DVI or HDMI receiver devices are provided. An HDCP transmitting apparatus according to the invention may include a computer and a look-up table accessible by the computer. The look-up table may include a database for storing an interoperability characteristic for an HDCP receiving device. The computer can communicate with the HDCP receiving device. The computer may also insert a delay in an initiation of the authentication and/or communication of content between the HDCP transmitting apparatus and the HDCP receiving device. The magnitude of the delay may be based on an interoperability characteristic retrieved from the look-up table that corresponds to the HDCP receiving device. The inserting may occur prior to the implementation of authentication initiation and ongoing link integrity checking between the transmitting apparatus and the HDCP receiving device.

Abstract: A system and method for using sequence ordered sets for energy efficient Ethernet communication. Sequence ordered sets can be generated by a first device for communication of parameter(s) to a second device, which parameters can be used in implementing an energy efficient Ethernet control policy. Sequence ordered sets can be used in communication between physical layer devices, or between a physical layer device and a media access control device. In one example, the sequence ordered set can identify a point at which a rate transition is to occur.

Abstract: A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.

Abstract: A transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the first or second interconnect layers. A second plurality of contacts connect the drain regions to the other of the first or second interconnect layers. The first and second interconnect layers cover a region above the substrate area in which the plurality of transistors reside so as to achieve a low ohmic result. The second interconnect layer has openings therein for one of the respective first or second plurality of contacts to pass therethrough and couple to the at least one first interconnect layer. Either the first or second interconnect layers can function as an input or output for the circuit.

Abstract: Methods and systems for gain control and power saving in broadband feedback low-noise amplifiers are disclosed and may include controlling gain, power and/or a noise figure by selectively enabling one or more of a plurality of gain stages by activating one or more of a plurality of pairs of switching transistors. Each of the gain stages may comprise complementary inverter pairs, with the gain of each of the gain stages binary weighted and stored in a lookup table. A feedback resistance coupled across the gain stages may be adjusted, and may comprise a plurality of individually addressable resistors, with the resistance binary weighted and stored in a lookup table. The adjusting of the feedback resistance may comprise switching one or more of a plurality of switching transistors, each connected in parallel with one of the individually addressable resistors, which may shunt one or more of the individually addressable resistors.

Abstract: In one aspect, there is provided a method for use by an edge device for establishing a connection with a server to support a full TCP connection between a client and the edge device. The method comprises establishing a full TCP connection with the server using a full TCP socket, allocating a first light TCP socket for supporting a first light TCP connection with the server, associating a first light session ID with the first light TCP connection, sending a first open session message to the server via the full TCP connection with the server, establishing the first light TCP connection with the server via the full TCP connection, associating first data with the first light session ID, and delivering the first data associated with the first light session ID to the server using the first light TCP connection via the full TCP connection.

Abstract: A method and system for frame formats for MIMO channel measurement exchange is provided. Aspects of a method for communicating information in a communication system may comprise transmitting data via a plurality of radio frequency (RF) channels utilizing a plurality of transmitting antenna, receiving feedback information via at least one of a plurality of RF channels, and modifying a transmission mode based on the feedback information. Aspects of a method for communicating information in a communication system may also comprise receiving data via a plurality of receiving antenna, transmitting feedback information via at least one of the plurality of RF channels, and requesting modification of a transmission mode for the received data in transmitted response messages comprising the feedback information.

Abstract: Digital signal processing based methods and systems for receiving optical data signals include parallel receivers, multi-channel receivers, timing recovery schemes, equalization schemes, and multi-path parallel receivers in which an analog-to-digital converter (“ADC”) and/or a digital signal processor (“DSP”) are implemented with parallel paths that operate at lower rates than the received data signal.

Abstract: An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the multiplexer. A common buffer may be coupled between the multiplexer and the pad to save substrate space. An analog circuit may be coupled to the pad to provide a signal path minimizing signal distortion. The integrated circuit's clock may be coupled via the multiplexer to an off-substrate circuit. Selective module coupling improves the integrated circuit's testing speed, may salvage an integrated circuit containing a malfunctioning module, and provides for signal loopback during testing.

Abstract: A direct memory access system utilizing a local memory that stores a plurality of DMA command lists, each comprising at least one DMA command. A command queue can hold a plurality of entries, each entry comprising a pointer field and a sequence field. The pointer field points to one of the DMA command lists. The sequence field holds a sequence value. A DMA engine accesses an entry in the command queue and then accesses the DMA commands of the DMA command list pointed to by the pointer field of the accessed entry. The DMA engine performs the DMA operations specified by the accessed DMA commands. The DMA engine makes available the sequence value held in the sequence field of the accessed entry when all of the DMA commands in the accessed command list have been performed. In one embodiment, the command queue is part of the DMA engine.

Abstract: A phase locked loop (PLL) with small size and improved performance is achieved using a type 1 PLL, a frequency detector and logic for switching between the type 1 PLL and frequency detector. The logic disables the type 1 PLL and enables the frequency detector to bring the frequency of a PLL output signal to within a frequency locking range of the type 1 PLL, and then disables the frequency detector and enables the type 1 PLL to lock the phase of the PLL output signal.

Abstract: A system and method for providing dynamic allocation of MIMO communication resources during a single communication. Various aspects of the present invention may comprise determining a first set of MIMO communication resources to utilize for communicating a first portion of a unit of information. The first set of MIMO communication resources may be allocated for communicating the first portion of the unit of information. A second set of MIMO communication resources may be determined to utilize for communicating a second portion of the unit of information, where the second set of MIMO communication resources is different from the first set of MIMO communication resources. The second set of MIMO communication resources may be allocated for communicating the second portion of the unit of information. The first and second portions of the unit of information may, for example, be communicated consecutively or concurrently.

Abstract: A system and method for management of bandwidth in a fiber optic, ethernet-based, TDMA communications system. A request/grant process is used to control the use of upstream bandwidth. A sense of time must therefore be shared by a headend and remote end-user devices. The invention provides for a gigabit media-independent interface in a media access controller to detect start-of-frame delimiters in incoming data. This allows for synchronization of a headend and end-user devices. The invention also allows for phase locking a transmit bit rate, at a headend, to the headend's clock. Transmitted data can the be used downstream to derive a local clock. Synchronization can also be maintained by the use of synchronization bytes in MPEG frames and/or variable length frames. Efficient bandwidth usage can also be facilitated by the use of maximum data units in allocating bandwidth in unsolicited grants, and by allowing flexible fragmentation and/or prioritization of internet protocol (IP) packets.

Abstract: A switch regulator module includes a switch and a current sensing module. The switch has an input port and an output port. The current sensing module senses a first voltage at the input port of the switch and a second voltage at the output port of the switch. The current sensing module generates a sense signal that is proportional to a current that flows through the switch based on the first and second voltages.

Abstract: A direct sampling tuner includes a low noise amplifier and an optional dynamically configurable band pass filter coupled to the low noise amplifier. The optional filter is configured to pass a selected band of channels. The tuner further includes a relatively high accuracy, multi-bit analog-to-digital converter (“ADC”) coupled to the LNA or to the optional dynamically configurable band pass filter. The ADC operates at greater than about twice a frequency of a sampled signal. The ADC directly samples the spectrum of the selected channels at the Nyquist frequency, thus avoiding image problems presented by conventional tuners.

Abstract: According to one exemplary embodiment, a memory array includes a memory cell having a programmable poly fuse coupled between a designated program node and a ground node, where the programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. In the programmable poly fuse, the P type resistive poly segment is coupled to the ground node and the N type resistive poly segment is coupled to the designated program node. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to the ground node. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to the designated program node.