Abstract: Certain aspects of a method and system for deferred pinning of host memory for stateful network interfaces are disclosed. Aspects of a method may include dynamically pinning by a convergence network interface controller (CNIC), at least one of a plurality of memory pages. At least one of: a hypervisor and a guest operating system (GOS) may be prevented from swapping at least one of the dynamically pinned plurality of memory pages.

Abstract: Provided is a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode.

Abstract: Methods and systems for extending the functionality of an embedded Universal Serial Bus (USB) transceiver interface to handle threshold shift of a USB 2.0 bus during high-speed chirp are presented. A method for a transceiver of a host coupled by a USB 2.0 bus to a device includes receiving a control signal, and selecting one of a first and second zero level voltage threshold according to the control signal. The first threshold is higher than the second to compensate for a shift in a zero level of the bus during high-speed chirp. In one example, the transceiver selects the first threshold when driving a reset signal, and selects the second threshold after detecting a device high-speed chirp signal. In another example, the transceiver selects the second threshold after driving a high-speed chirp sequence. In one example, the control signal includes a signal of a host controller embedded USB transceiver interface.

Abstract: Various embodiments are disclosed relating to wireless receivers. According to an example embodiment, a method and apparatus are provided. The method may include receiving an input signal within a first frequency range (e.g., RF). The input signal may include a desired signal and a blocker signal. The method may also include down-converting the input signal to a second frequency range (e.g., IF) that is lower than the first frequency range, separating the blocker signal from desired signal (e.g., at the second frequency range), up-converting the separated blocker signal to the first frequency range (e.g., RF), and subtracting the up-converted blocker signal from the input signal.

Abstract: A linear high powered integrated circuit amplifier includes a plurality of power amplifiers, balanced integrated circuit coupling, and a combining circuit. The balanced integrated circuit coupling couples a signal to the plurality of power amplifiers to the up-conversion module such that the power amplifiers amplify the signal to produce a plurality of amplified radio frequency (RF) signals. The combining circuit is operably coupled to combine the plurality of amplified RF signals to produce a high-powered amplified signal.

Abstract: A re-assembly buffer for use in interim storage of aligned data and to reassemble data output onto a wider internal data path, in which the width of the data path is determined to have sufficient bandwidth to account for frequency scaling of received data rate to frequency of the data path and fragmentation of data for alignment onto the data path. The buffer may be is arranged into arrays using single read port, single write port memory devices.

Abstract: A transconductance stage providing gain control includes an input stage to convert a first differential input voltage and a second differential input voltage to a first intermediate current and a second intermediate current, respectively. An output stage generates a first output current signal and a second output current signal based on the first and second intermediate currents, respectively. The output stage includes a first plurality of output transistors coupled to a first plurality of corresponding switch resistors and a second plurality of output transistors coupled to a second plurality of corresponding switch resistors. The number of activated switch resistors of the first plurality of switch resistors determines a gain of the first output current signal and a number of activated switch resistors of the second plurality of switch resistors determines a gain of the second output current signal.

Abstract: A miniMAC implementation of a distributed CMTS in a hybrid fiber/coaxial (HFC) plant. The distributed CMTS comprises at least one network layer, at least one media access layer, and one or more physical layers. The at least one media access layer includes one or more miniMAC layers. The one or more miniMAC layers are remotely located from a remaining part of the at least one media access layer. The at least one network layer, the remaining part of the at least one media access layer, the one or more miniMAC layers, and the one or more physical layers each function as separate modules, enabling each layer to be in separate component locations of the HFC plant, yet having the at least one network layer connected to the remaining part of the at least one media access layer, the at least one media access layer connected to each of the one or more miniMAC layers, and each of the one or more physical layers connected to each of the one or more miniMAC layers.

Abstract: Aspects of a method and system for polar modulation with discontinuous phase for RF Transmitters with power control may include amplifying a signal via a plurality of amplifiers such that a combined gain of the plurality of amplifiers comprises a coarse amplitude gain, a power level gain and an amplitude offset gain. A gain of one or more of the plurality of amplifiers may be adjusted to set the coarse amplitude gain and the power level gain. A gain of one or more remaining ones of the plurality of amplifiers may be adjusted to set the amplitude offset gain. The setting of the coarse amplitude gain, the power level gain and/or the amplitude offset gain may be adjusted dynamically and/or adaptively.

Abstract: A voltage supply interface provides both coarse and fine current control with reduced series resistance. The voltage supply interface has a segmented switch having N component switches that are digitally controlled. The voltage supply interface replaces a conventional sense resistor with a calibration circuit that has a replica switch that is a replica of the N component switches. The calibration circuit includes a reference current IREF that is sourced through the replica switch. A feedback amplifier forces a common voltage drop across the replica switch and the n-of-N activated component switches so that the cumulative current draw through the segmented switch is n·IREF. The current control of the voltage interface can be coarsely tuned by activating or deactivating component switches, and can be finely tuned by adjusting the reference current. The current sense resistor is eliminated so that the overall series resistance is lower.

Abstract: De-jittering a transport stream, at least some transport packets of the transport stream carrying audio-video data and at least some of the transport packets of the transport stream containing Program Clock References (PCRs). A data buffer receives the transport packets and stores the transport packets. Pacing counter clock circuitry produces a pacing counter clock and adjusts the pacing counter clock based upon a pacing counter clock adjust signal. Pacing control circuitry produces the pacing counter clock adjust signal based upon receipt of the transport packets. PCR packet pacing circuitry receives the pacing counter clock, based upon the packing counter clock, retrieves transport packets from the data buffer, and transmits the retrieved transport packets as an output transport stream. The pacing counter clock adjust signal may be based upon data buffer fullness or based upon an estimated program clock generated from the PCRs.

Abstract: An apparatus comprising a managed network interface configured to receive data from, and transmit data to, a managed network, wherein the managed network comprises a plurality of managed devices configured to queue and transmit data; an unmanaged network interface configured to receive data from, and transmit data to, an unmanaged network, wherein the unmanaged network is configured to request the amelioration of network congestion experienced by the unmanaged network; and a congestion manager configured to receive a network congestion amelioration request from the unmanaged network, ameliorate network congestion by controlling the rate of information forwarded from the managed network to an unmanaged network, and dynamically alter the rate of information forwarded from the managed network to the unmanaged network.

Abstract: A transmitter includes a dual mode modulator and an amplifier coupled to the dual mode modulator. The dual mode modulator implements a linear modulation scheme during a first mode of the modulator to produce a variable envelope modulated signal. The dual mode modulator implements a non-linear modulation scheme during a second mode of the modulator to produce a constant envelope modulated signal. The amplifier is biased as a linear amplifier during the first mode of the modulator and is biased as a non-linear amplifier during the second mode of the modulator. A feed-forward connection between the dual mode modulator and the amplifier is used to indicate a change in modulation mode and to adjust the bias of the amplifier. A power of the constant envelope modulated signal is increased such that an operating point of the amplifier remains substantially constant during the first and second modes of the modulator.

Abstract: Certain aspects of a method and system for implementing a codec may comprise at least one of inverse discrete cosine transforming windowed data corresponding to a plurality of input audio samples during encoding by a Bluetooth subband codec and discrete cosine transforming shifted subband samples during decoding by the Bluetooth subband codec. The input audio samples may be reconstructed from the discrete cosine transforming of the shifted subband samples. The inverse discrete cosine transforming may be executed during a matrix operation of the encoding. The discrete cosine transforming may be executed during a matrix operation of the decoding. The input audio samples may be windowed during the encoding via a plurality of delay lines. A vector may be generated during a matrix operation of the decoding. The audio data associated with the generated vector may be windowed by a plurality of filter coefficients via a plurality of delay lines.

Abstract: In accordance with the present invention a system for detecting transaction errors in a system comprising a plurality of data processing devices using a common system interconnect bus, comprises a node controller operably connected to said system interconnect bus and a plurality of interface agents communicatively coupled to said node controller. Error corresponding to transactions between said interface agents and other processing modules in said system are directed to said node controller; and wherein transaction errors that would not normally be communicated to said system interconnect bus are communicated by said node controller to said system interconnect bus to be available for detection. In an embodiment of the present invention, the interface agents operate in accordance with the hypertransport protocol. A system control and debug unit and a trace cache operably connected to the system bus can be used to diagnose and store errors conditions.

Abstract: A system and method for providing a low power warning in a portable communication device based on predicted device utilization. Various aspects of the present invention may comprise monitoring power utilization for a portable communication device. A power utilization profile may be determined based, at least in part, on the results of the power utilization monitoring. Power availability for the portable communication device may be determined. Future power need for the portable communication device may be predicted based, at least in part, on the determined power utilization profile. The predicted future power need and the determined power availability may be analyzed to determine whether to generate a warning indicating a potential future power shortage. If it is determined that a potential future power shortage warning should be generated, such a warning may be generated. Such a warning may, for example, be generated in accordance with user specifications.

Abstract: Construction of Irregular LDPC (Low Density Parity Check) codes using RS (Reed-Solomon) codes or GRS (Generalized Reed-Solomon) codes. As described herein, a wide variety of irregular LDPC codes may be generated using GRS or RS codes. The corresponding LDPC matrix of such an irregular LDPC code may be constructed by performing partial-matrix processing (including decomposition and partial-matrix replacement thereof) of a parity check matrix that corresponds to a GRS-based regular LDPC code. Such an irregular LDPC code may be appropriately designed using these principles thereby generating a code that is suitable for use in wireless communication systems including those that comply with the recommendation practices and standards being developed by the IEEE (Institute of Electrical & Electronics Engineers) 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.11 TGn (High Throughput)).

Abstract: A system and method for concealing input parameters that are being loaded into a device. In one embodiment, the system provides a transformed interface, in which a device inverse transformation keys. The parameters to be concealed are transformed using a particular key, along with a transformed index value to indicate the particular key that must be used to inversely transform parameter.

Abstract: A system and method for interference reduction in a spread spectrum receiver including a rake receiver having a plurality of fingers for processing a plurality of data signals and an associated plurality of pilot signals is disclosed herein. The method includes generating a plurality of intra-finger interference cancellation signals using the plurality of pilot signals. In this regard each of the plurality of intra-finger interference cancellation signals are associated with one of the plurality of fingers. Ones of the plurality of intra-finger interference cancellation signals are weighted so as to generate a set of weighted intra-finger interference cancellation signals. The method further includes synthesizing at least one inter-finger interference cancellation signal in accordance with the set of weighted intra-finger cancellation signals. At least one inter-finger cancellation signal may then be subtracted from a corresponding one of a plurality of data signals.

Abstract: An exemplary embodiment of the present invention described and shown in the specification and drawings is a transceiver with a receiver, a transmitter, a local oscillator (LO) generator, a controller, and a self-testing unit. All of these components can be packaged for integration into a single IC including components such as filters and inductors. The controller for adaptive programming and calibration of the receiver, transmitter and LO generator. The self-testing unit generates is used to determine the gain, frequency characteristics, selectivity, noise floor, and distortion behavior of the receiver, transmitter and LO generator. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.