Abstract: A method determines RW head radial position relative to tracks within a magnetic data disc. This involves sensing both a S-burst signal and a P-burst signal with the RW head. The S-burst signal and P-burst signal are associated with a two-burst servo pattern on the magnetic disc. The S-burst pattern has a phase that remains constant radially across tracks within the magnetic disc. The P-burst has a second phase that rotates radially across tracks within the magnetic disc. By determining a phase difference between a sensed S-burst signal and P-burst signal, it is possible to determine the RW head radial position relative to the tracks on the magnetic disc.

Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.

Abstract: Discrete multitone transmission assigns bits to tones for transmission. The bits are assigned using permutations of bits and tones that cycle through a sequence of permutations in successive frames.

Abstract: A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages. The second pipeline includes a second stage at which an exception is reportable, wherein the second stage is separated from the issue stage of the second pipeline by a second number of stages which is greater than the first number. The control circuit is configured to inhibit co-issuance of a first instruction to the first pipeline and a second instruction to the second pipeline if the first instruction is subsequent to the second instruction in program order.

Abstract: A frame format for high data throughput wireless local area network transmissions includes a first preamble segment, a second preamble segment, and a variable length data segment. The first preamble segment includes a first training sequence, a second training sequence, and a high throughput channel indication, wherein the first training sequence is within a first set of subcarriers of a channel and the second training sequence is within a second set of subcarriers of the channel, wherein the first set of subcarriers is a subset of the second set of subcarriers. The second preamble segment includes a third training sequence within a third set of subcarriers of the channel, wherein the second set of subcarriers is a subset of the third set of subcarriers. The variable length data segment utilizes the third set of subcarriers to convey data.

Abstract: A motion detector (300) detects motion of images represented by video pixels by providing a memory (19) arranged to store first pixels processed during a first time period. The motion detector (300) responds to differences between the first pixels and second pixels processed during a second time period after the first time period to generate initial motion signals. A look up table (362) and an edge detector (364) modify the initial motion signals to generate the output motion signals.

Abstract: An interface which effects communication between first and second systems and includes a first arrangement for communicating with the first system using a first protocol and a second arrangement for communicating with the second system using a second protocol. At least one of the arrangements includes a mechanism for effecting wireless communication. In accordance with the invention, a third arrangement is included for translating data received from the first system in accordance with the first protocol into data adapted for the second system in accordance with the second protocol. In the illustrative embodiment, the inventive interface further includes an arrangement for translating data received from the second system in accordance with the second protocol into data adapted for the first system in accordance with the first protocol.

Abstract: A method for compensating a power amplifier based on operational-based changes begins by measuring one of a plurality of operational parameters of the power amplifier to produce a measured operational parameter. The method continues by comparing the measured operational parameter with a corresponding one of a plurality of desired operational parameter settings. The method continues by, when the comparing of the measured operational parameter with the corresponding one of a plurality of desired operational parameter settings is unfavorable, determining a difference between the measured operational parameter and the corresponding one of a plurality of desired operational parameter settings. The method continues by calibrating the one of the plurality of operational settings based on the difference.

Abstract: A transconductance device has substantially linear characteristics. The transconductance device includes a differential pair that receives a differential input voltage signal and produces a differential output current signal and a current source coupled to the differential pair. The current source produces a current having a constant portion and a variable portion, such that the derivative of the transconductance with respect to the differential input voltage is constant across a very large range of the differential input voltage and across a very high range of frequencies of the differential input signal. This linearization technique produces no extraneous noise at the differential output current.

Abstract: A transceiver front end includes a transmit/receive (T/R) switch, a first balun, a second balun, a low noise amplifier, a power amplifier, and compensation circuitry. The T/R switch is operably coupled to an antenna for receiving inbound radio frequency (RF) signals and for transmitting outbound RF signals. The first balun includes a single ended winding and a differential winding, where the single ended winding is operably coupled to the T/R switch. The second balun includes a single ended winding and a differential winding, where the single ended winding is operably coupled to the T/R switch. The low noise amplifier is operably coupled the differential winding of the first balun. The power amplifier is operably coupled to the differential winding of the second balun. The compensation circuitry is operably coupled to the first balun to compensate for at least one of phase imbalance, amplitude imbalance, and impedance imbalance of the first balun.

Abstract: A memory controller includes a plurality of channel control circuits. Each of the plurality of channel control circuits is coupled to a respective one of a plurality of channels which are coupled to a memory system. The plurality of channel control circuits are coupled to receive an indication of whether or not the plurality of channels are ganged. Data is transferred for a first command on each of the plurality of channels responsive to the indication indicating that the plurality of channels are ganged. Responsive to the indication indicating that the plurality of channels are not ganged, data is transferred for the first command on a selected channel of the plurality of channels. In some embodiments, the memory controller may be integrated with one or more processors.

Abstract: Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

Abstract: A system and method for compensating for process, voltage, and temperature variations in a circuit is provided. A system includes an inverter having an input port, and an output port, and is configured to (i) receive an input signal, (ii) delay the received input signal, and (iii) provide the delayed signal to the inverter output port. The system also includes a logic device including at least two input ports and an output port. A first of the at least two input ports is configured to receive the delayed signal. Finally, the system includes a charge storing device having a first end coupled, at least indirectly, to a second of the at least two input ports and a second end coupled to a logic device common node. The charge storing device is configured to (i) receive the input signal and (ii) sense a rate of change in voltage of the received input signal, the sensed voltage being representative of a corresponding current.

Abstract: An apparatus comprises a first plurality of buffers configured to store operations belonging to a first virtual channel and a control circuit coupled to the first plurality of buffers. The first virtual channel includes first operations and second operations, wherein each of the first operations depend on at least one of the second operations during use. A first number of the first operations is less than or equal to a maximum. It is ambiguous, for a first received operation in the first virtual channel, whether the first received operation is one of the first operations or the second operations. A total number of the first plurality of buffers exceeds the maximum.

Abstract: A transceiver for combining RFID amplitude-modulated data with wireless phase-modulated data is realized by a processing module operably coupled to generate outbound non-amplitude modulated symbols from first outbound data, to generate outbound amplitude modulated symbols from second outbound data, to generate first inbound data from inbound non-amplitude modulated symbols, and to generate second inbound data from inbound amplitude modulated symbols, a combiner operably coupled to modulate the amplitude modulated symbols onto a signal carrying the non-amplitude modulated symbols to produce a combined outbound RF signal and a splitter operably coupled to convert a combined inbound RF signal into inbound non-amplitude modulated symbols and into inbound amplitude modulated symbols.

Abstract: In a wireless communication system, dynamic payload header suppression (DPHS) is applied to a data stream to reduce header overhead. DPHS allows the suppression of static fields as well as fields that change in a predictable manner (i.e., predictably dynamic fields). To suppress predictably dynamic fields, delta encoding is utilized to enable a cable modem to replace a dynamic field with information indicating how the field is different from the same field in a previous packet in the data stream. DPHS constructs a suppression mask by using a special packet called a “learn” packet. The “learn” packet is a copy of the original packet with extra bytes that guide the suppression process. It indicates that both the sending and receiving entities are to take a full copy of a packet header, which is then used as a reference to reconstruct the suppressed fields.

Abstract: An integrated RFID reader and wireless communication device is realized by a radio frequency (RF) front end operable, in a first mode, to generate a radio frequency identification system (RFID) outbound radio frequency (RF) signal, to receive an RFID inbound RF signal responsive to the RFID outbound RF signal and to convert the RFID inbound RF signal to an RFID near baseband signal, and operable in a second mode, to generate a transceiver outbound radio frequency (RF) signal, to receive a transceiver inbound RF signal and to convert the transceiver inbound RF signal to a transceiver near baseband signal.

Abstract: A transceiver is described that includes a power amplifier (PA), a low noise amplifier (LNA), and an impedance matching circuit having a first and second differential output node. The first and second differential output nodes are coupled to outputs of the PA and to inputs of the LNA. The impedance matching circuit provides a load impedance to the outputs of the PA. The transceiver further includes a first impedance device having an output impedance coupled between the first and second differential output nodes. In this way, the combination of the output impedance and the load impedance matches with an impedance at the inputs of the LNA.

Abstract: A radio receiver is described that processes multiple wireless standards using a single antenna according to embodiments of the invention. The radio receiver includes a single antenna, and a low noise amplifier that is connected to the antenna, without an intervening power divider or power splitter. The output of the low noise amplifier feeds multiple wireless receivers in a parallel arrangement that are operating according to different communications standards, including for example a Bluetooth and a WLAN 802.11. Additional wireless standards and their corresponding receivers could be added as well. The input impedance of the low noise amplifier defines the impedance seen by the antenna, regardless of which operational standard is actually in use. Each signal path includes an additional low noise amplifier having a gain that can be customized for the particular signal path and receiver in use, and which also improves the reverse isolation between signal paths.

Abstract: A highly integrated and low-cost reader for a radio frequency identification (RFID) system is realized by providing a transmitter operable to generate an outbound radio frequency (RF) signal and a receiver operable to receive an inbound RF signal having a frequency similar to a frequency of the outbound RF signal on a single integrated circuit. Since the inbound RF signal may include not only a modulated RF signal produced by an RFID tag responsive to the outbound RF signal, but also a blocking signal corresponding to the outbound RF signal, the receiver additionally includes a block cancellation module operable to substantially cancel the blocking signal from the inbound RF signal using the outbound RF signal and to substantially pass the modulated RF signal before down-conversion of the modulated RF signal.