Abstract: A system for calculating DC offset and achieving frame detection is described. In one embodiment, the present invention includes an electronic device with an integrated receiver module. The receiver module can take advantage of a known synchronization pattern such as the Bluetooth access code to determine an initial DC offset and to provide frame detection.

Abstract: An integrated circuit containing multiple modules coupled to a pad via a multiplexer. The modules are selectively coupled to the pad by the multiplexer to provide integrated circuit function flexibility with a limited number of pads. A multiplexer select signal determines which module or clock circuit is coupled by the multiplexer. A common buffer may be coupled between the multiplexer and the pad to save substrate space. An analog circuit may be coupled to the pad to provide a signal path minimizing signal distortion. The integrated circuit's clock may be coupled via the multiplexer to an off-substrate circuit. Selective module coupling improves the integrated circuit's testing speed, may salvage an integrated circuit containing a malfunctioning module, and provides for signal loopback during testing.

Abstract: A wireless terminal displays its location and navigation information (map segment) on its display. The wireless terminal accesses a Global Positioning System (GPS) receiver of the wireless terminal to determine its location coordinates. The wireless terminal determines a maximum data size for navigation information to be downloaded. The wireless terminal sends a navigation information download request to a map server via a supporting wireless network infrastructure that includes the location coordinates and the maximum data size. The wireless terminal receives navigation information that has a data size no greater than the maximum data size and displays the navigation information on the display. The wireless terminal may display a map segment and an icon representing the wireless terminal at a location corresponding to the location coordinates of the wireless terminal with respect to the map segment. The wireless terminal may download a premises map from a premises map server.

Abstract: A receiver in a wireless local area network capable of receiving and processing plurality of frames that are separated by a reduced interframe spacing interval. . Upon receiving a frame, the receiver determines whether the received frame is using Reduced Interframe Spacing intervals. When the received frame includes a RIFS indicator, acknowledgment of the received frame is suppressed, and subsequent frames of the plurality of frames are received at a RIFS interval.

Abstract: A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes at least one processing device, an IR processing function, and IR memory. The at least one processing device is operable to receive analog signals corresponding to a data block, to sample the analog signals to produce samples, to equalize the samples to produce soft decision bits corresponding to the data block, and to initiate IR operations. The IR processing function is operable to perform IR operations on the soft decision bits of the data block in an attempt to correctly decode the data block. The IR memory operably couples to the IR processing function, includes Type I IR memory adapted to store IR status information of the data block, and includes Type II IR memory adapted to store the data block.

Abstract: An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially equal to either the voltage input signal or ground, depending on whether the voltage input signal has reached a threshold voltage. The threshold voltage is defined by component characteristics of the main detector core and the two-inverter buffer block. The circuit can receive a hysteresis input signal, tied to the voltage input signal or the ground, that allows the threshold voltage to have a first threshold value when the voltage input signal increases and a second threshold value when the voltage input signal decreases. A power down input signal can also be received that allows the circuit to be powered down.

Abstract: A voltage interpolation circuit includes a resistive ladder connected between ground and a voltage input and having a plurality of resistors with voltage taps between the resistors. An amplifier (optionally) has first and second capacitors connected together at their respective first terminals and to an input of the amplifier. A first plurality of switches connect respective taps to a second terminal of the first capacitor. A second plurality of switches connect the respective taps to a second terminal of the second capacitor. An output voltage is interpolated by controlling the first and second pluralities of switches.

Abstract: Computer-implemented method and system for generating an optimized description of an arithmetic function comprising at least two of an addition, a multiplication, and a rounding operation to be carried out on a plurality of data bits in a plurality of registers of an electronic circuit, the method comprising the steps: obtaining a first description of the arithmetic function; decomposing the first description to obtain a second description comprising individual binary and logical operations on data bits, wherein the data bits are arranged to their proper place value, the second description being substantially arithmetically equivalent to the first description; obtaining a third description by parallelizing at least two of the binary and logical operations on the data bits in the second description; providing a forth description comprising operations for each data bit comprised in the third description in a hardware description language as the optimized description of the electronic circuit.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: A system and method for interleaving data in a wireless transmitter wherein bits from the input data stream are sent to downstream processing without being stored in memory. According to a first example embodiment of the present invention, a first radio frame of data from an input code block is sent downstream, and the remaining radio frames from the code block are stored in the memory buffer. The first interleaving pattern can be applied, for example, as data is written to or read from the memory buffer. The stored radio frames are then read out as needed by the downstream processing. According to a second example embodiment of the present invention, further savings in memory can be achieved by discarding bits that are not currently needed for processing then recalculating them at a later time. A first radio frame of data from an input code block is sent downstream without being stored in the memory buffer.

Abstract: A system for servicing data transactions within a processing device using common data paths. The system is broadly comprised of: a plurality of source agents operable to transmit a plurality of data cells; a plurality of destination agents operable to of data cells; a plurality of virtual channels for transporting data cells between the source agents and the destination agents; and a switch. The switch is operable to connect predetermined combinations of the source agents and the destination agents for the transmission of data. The switch generates a plurality of switch processing cycles and processes a plurality of control signals during the switch processing cycles.

Abstract: A flip chip package generally includes a substrate, a flip chip die, and a heat spreader. The flip chip die is coupled to the substrate. The heat spreader is coupled to the flip chip die. The heat spreader can include one or more walls. Generally, the one or more walls at least partially laterally surround the flip chip die and/or the substrate. The walls can completely laterally surround the flip chip die to define a cavity in the heat spreader. The flip chip package can further include an encapsulate. For example, the encapsulate can be injected between the one or more walls of the heat spreader and the flip chip die and/or other components of the flip chip package. The encapsulate and/or the one or more walls of the heat spreader can protect one or more components of the flip chip package against moisture, corrosives, heat, or radiation, to provide some examples.

Abstract: Provided is a system for operating a communication device (20) for reception of scheduled intermittent information messages (22) with a dual mode timer (70) that extends battery life. A controller (50) schedules the timer (70) to power down all idle components of the device (20) between message receptions in a power saving sleep mode to conserve battery power. During active mode when the device is fully active in reception of messages, the timer (70) uses a reference oscillator (90) with a relatively high frequency to support digital processing by the receiver (26). During sleep mode when only the timer is powered on, a much lower frequency sleep oscillator (96) is used to maintain the lowest possible level of power consumption within the timer itself. The timer (70) has provision for automatic temperature calibration to compensate for timing inaccuracies inherent to the low-power low-frequency crystal oscillator (96) used for the sleep mode.

Abstract: An integrated circuit (IC) low noise amplifier includes an on-chip balun and an on-chip differential amplifier. The on-chip balun is coupled to convert a single-ended signal into a differential signal. The on-chip differential amplifier is coupled to amplify the differential signal.

Abstract: A transconductance stage providing gain control includes an input stage to convert a first differential input voltage and a second differential input voltage to a first intermediate current and a second intermediate current, respectively. An output stage generates a first output current signal and a second output current signal based on the first and second intermediate currents, respectively. The output stage includes a first plurality of output transistors coupled to a first plurality of corresponding switch resistors and a second plurality of output transistors coupled to a second plurality of corresponding switch resistors. The number of activated switch resistors of the first plurality of switch resistors determines a gain of the first output current signal and a number of activated switch resistors of the second plurality of switch resistors determines a gain of the second output current signal.

Abstract: Magnetic reference patterns may be generated on a disk or other magnetic media without the need for seed wedges. This involves writing a first magnetic reference pattern to the disk with a servo writer. The disk may then be transferred to a hard disk drive. Control circuitry within the hard disk drive may recognize the first magnetic reference pattern and then position a RW head within the hard disk drive based on the first magnetic reference pattern. As the RW drive is accurately positioned based on the first magnetic reference pattern a second magnetic reference pattern may be written to the disk using the RW head. The RW head location is determined based on the velocity and phase between the read-write head and servo setter marks contained within the first magnetic reference pattern.

Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Abstract: A multipath wireless communication is processed to recover a transmitted data signal without performing a direct matrix inversion (DMI). First, the multipath wireless communication is received. Then HHH and HHH values associated with the multipath wireless communication are determined. Weights based on HHH and HHH associated with the received data signal may then be determined and used to recover the transmitted data signal from the received multipath wireless communication.

Abstract: In a wireless communication system, dynamic payload header suppression (DPHS) is applied to a data stream to reduce header overhead. DPHS allows the suppression of static fields as well as fields that change in a predictable manner (i.e., predictably dynamic fields). To suppress predictably dynamic fields, delta encoding is utilized to enable a cable modem to replace a dynamic field with information indicating how the field is different from the same field in a previous packet in the data stream. DPHS constructs a suppression mask by using a special packet called a “learn” packet. The “learn” packet is a copy of the original packet with extra bytes that guide the suppression process. It indicates that both the sending and receiving entities are to take a full copy of a packet header, which is then used as a reference to reconstruct the suppressed fields.

Abstract: An integrated circuit power supply includes a DC-to-DC converter and a low drop-out voltage regulator. The DC-to-DC converter efficiently performs voltage conversion and provides power to the low-dropout voltage regulator. The low-dropout voltage regulator rejects noise and regulates an output voltage. The combination of the DC-to-DC converter and a low-dropout voltage regulator provides high-efficiency voltage conversion and noise rejection.