Abstract: A transceiver is described that includes a power amplifier (PA), a low noise amplifier (LNA), and an impedance matching circuit having a first and second differential output node. The first and second differential output nodes are coupled to outputs of the PA and to inputs of the LNA. The impedance matching circuit provides a load impedance to the outputs of the PA. The transceiver further includes a first impedance device having an output impedance coupled between the first and second differential output nodes. In this way, the combination of the output impedance and the load impedance matches with an impedance at the inputs of the LNA.

Abstract: Power over Ethernet (PoE) communication systems provide power and data communications over the same communications link, where a power source device (PSE) provides DC power (for example, 48 volts DC) to a powered device (PD). The DC power is transmitted simultaneously over the same communications medium with the high speed data from one node to the other node. The PSE typically includes a controller that controls the DC power provided to the PD at the second node of the communications link. The PSE controller measures the voltage, current, and temperature of the outgoing and incoming DC supply lines to characterize the power requirements of the PD. In addition, the PSE controller may detect and validate a compatible PD, determine a power classification signature for the validated PD, supply power to the PD, monitor the power, and reduce or remove the power from the PD when the power is no longer requested or required.

Abstract: A radio receiver is described that processes multiple wireless standards using a single antenna according to embodiments of the invention. The radio receiver includes a single antenna, and a low noise amplifier that is connected to the antenna, without an intervening power divider or power splitter. The output of the low noise amplifier feeds multiple wireless receivers in a parallel arrangement that are operating according to different communications standards, including for example a Bluetooth and a WLAN 802.11. Additional wireless standards and their corresponding receivers could be added as well. The input impedance of the low noise amplifier defines the impedance seen by the antenna, regardless of which operational standard is actually in use. Each signal path includes an additional low noise amplifier having a gain that can be customized for the particular signal path and receiver in use, and which also improves the reverse isolation between signal paths.

Abstract: Providing wireless transmission, where in a first transmission mode, transmitting a plurality of frames using a first interframe spacing interval. When in a second transmission mode, transmitting the plurality of frames using a second interframe spacing interval, wherein the second interframe spacing is less than the first interframe spacing.

Abstract: A wireless communication device is provided with both a transceiver and a low-cost RFID reader. The RFID reader is operable to generate a first outbound radio frequency (RF) signal from first outbound data, to receive a first inbound RF signal responsive to the outbound RF signal and to convert the first inbound RF signal into inbound RFID digital data. The transceiver is operable to generate a second outbound radio frequency (RF) signal, to receive a second inbound RF signal and to convert the second inbound RF signal into inbound transceiver data.

Abstract: Optimizing a radio link is done by acquiring at least OSI layer one and two performance measurements, determining an optimum setting collection for at least OSI layer three to a top layer, then configuring at least the OSI layer three to the top layer based upon the optimum setting collection. The top layer is at least OSI layer four. The invention includes optimized radio links, methods of making optimized radio links, revenue generating making optimized radio links by providing means for optimizing the radio link.

Abstract: A radio receiver is described that processes multiple wireless standards using a single antenna according to embodiments of the invention. The radio receiver includes a single antenna, and a low noise amplifier that is connected to the antenna, without an intervening power divider or power splitter. The output of the low noise amplifier feeds multiple wireless receivers in a parallel arrangement that are operating according to different communications standards, including for example a Bluetooth receiver, and a WLAN 802.11 receiver. Additional wireless standards and their corresponding receivers could be added as well. The input impedance of the low noise amplifier defines the impedance seen by the antenna, regardless of which operational standard is actually in use. Since the input impedance of the low noise amplifier is substantially independent of whether the Bluetooth or WLAN paths are ON or OFF, simultaneous operation can be accomplished.

Abstract: Physical layer (PHY) sub-channel processing. A soft symbol decision stream is arranged into a number of sub-channels to reduce substantially the processing performed within a communication receiver on data that is not intended for that communication receiver. In other embodiments, a predetermined approach is employed to arrange the soft symbol decision stream into one or more frames; each frame may have one or more soft symbol blocks; and each soft symbol block may have one or more symbols. Each of the soft symbol blocks, within a frame, may be assigned to a sub-channel. Only the soft symbol blocks that contain information destined for the communication receiver need be decoded. Only the sub-channel that includes these soft symbol blocks, destined for this communication receiver, need be decoded. The soft symbol blocks not within the sub-channel may be discarded thereby recovering some of the processing capabilities of the communication receiver.

Abstract: An RF communications circuit having a reduced LO feed through image reject mixer is disclosed. The image reject mixer includes a quadrature phase transconductance stage coupled to a quadrature phase mixer of a quadrature phase mixer module and an in-phase mixer of an in-phase mixer module. The image reject mixer further includes an in-phase transconductance stage coupled to an in-phase mixer of the quadrature phase mixer module and a quadrature phase mixer of the in-phase mixer module. The output of the quadrature phase mixer and in-phase mixer of the quadrature phase mixer module are cross-coupled to form a quadrature phase local oscillator (LO) output and wherein the output of the quadrature phase mixer and in-phase mixer of the in-phase mixer module are cross-coupled to form an in-phase local oscillator (LO) output.

Abstract: A phase interpolator includes a plurality of clock phase input sections, a plurality of clock phase switching sections, a plurality of current sources and a load. Each of the clock phase input sections is coupled to receive one of a plurality of reference clock phases (e.g., 0°, 90°, 180°, and 270°). The plurality of current sources is selectively coupled to the plurality of clock phase input sections via the clock phase switching sections based on a phase control signal. The number of current sources corresponds to the phase granularity between the reference clock phases. The load is coupled to a phase adjusted clock signal in accordance with the phase control signal.

Abstract: A method and an apparatus for retiming in a network of multiple context processing elements in a network of multiple context processing elements are provided. A programmable delay element is configured to programmably delay signals between a number of multiple context processing elements of an array without requiring a multiple context processing element to implement the delay. The output of a first multiple context processing element is coupled to a first multiplexer and to the input of a number of serially connected delay registers. The output of each of the serially connected registers is coupled to the input of a second multiplexer. The output of the second multiplexer is coupled to the input of the first multiplexer, and the output of the first multiplexer is coupled to a second multiple context processing element. The first and second multiplexers are provided with at least one set of data representative of at least one configuration memory context of a multiple context processing element.

Abstract: A complex filter such as the channel select filter in a radio transceiver is implemented using a transconductance/C topology to benefit from the ability to tune such filters and thereby stabilize the output transfer function of the filter over variations in temperature, power supply voltage and process. The topology is based on an active R/C biquadratic topology to achieve the additional benefit of independently controlled stages. The problem created by the R in the output impedance is can be overcome by separately tuning the R value along with the transconductance/C ratio, by implementing the R as a transconductance amplifier having common mode feedback, or by implementing the transconductance amplifiers of the topology using Nauta transconductors, and unbalancing the common mode circuit of the Nauta transconductor to achieve a differential resistance that can be used to implement the R in the output impedance.

Abstract: In one embodiment of the present invention, two crystal oscillator circuits are coupled in parallel to provide differing performance according to mode. Generally, a first circuit provides low phase noise and high accuracy while a second circuit provides greater phase noise within an acceptable tolerance while consuming significantly less power in a low power mode of operation. The second circuit includes an entirely separate amplifier for the low power operation that tolerates a relatively smaller input signal swing but that consumes even less power. The first circuit, which comprises selectable amplification elements, and the second circuit are coupled in parallel with selectable resistive elements and capacitive elements to provide varying amounts of amplification and filtering according to whether an operational mode is in a startup mode, a normal mode, or a low power mode of operation.

Abstract: A hand held radio host includes circuitry for selectively providing power to radiating transceiver elements and non-radiating application elements according to a plurality of power modes of operation to achieve desired effects and in a way that saves power and extends battery life. In one embodiment of the invention, the hand held host operates in one of three modes. In a full power mode, any selected application element as well as all transceiver elements are powered on at the same time. Thus, for example, a cell phone module, a wireless personal access network module, a wireless local area network module and one of a pager/short message service message module may all be powered on at the same time to receive corresponding messages, calls, data sessions, etc. At the same time that all of the transceiver elements are powered on, any selected application element receives power. Thus, application elements such as address books, calendar functions, games, word processors, etc may receive power when selected.

Abstract: A method for packaging a radio frequency integrated circuit (RFIC) in multiple packages begins by determining a 1st position of the RFIC die in a 1st package wherein the positioning is such to minimize adverse affects of parasitic components of coupling between the radio frequency input/output section and an antenna. Once the position within the 1st package has been determined, the corresponding parasitics are measured to determine their values. The processing then continues by determining a 2nd position of the RFIC die in a 2nd package based on the values of the parasitic components. Accordingly, the 2nd position places the die within the 2nd package such that the parasitic components of coupling between the RF I/O section to the antenna within the 2nd package substantially matches the parasitic components of coupling the RFIO section to the antenna in the 1st package. Accordingly, different packages may be used with the same RFIC die, while maintaining the desired noise reduction.

Abstract: A data slicer for an FSK demodulator employs a peak and valley detector, each of which has a discharge path with selectable decay rates. The faster decay rate for the peak and valley detector outputs is selected when the difference between the current peak and valley voltages exceeds a predetermined percentage of the expected swing of the voltage input and when a packet has not been detected. When a packet is detected, a slower decay rate is selected. In this mode, the faster decay rate permits faster acquisition of packet data in the presence of DC offset, as it permits the data slicer to converge on an appropriate switching point more quickly.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS)technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.

Abstract: A method, apparatus, and computer program product for balancing transmission unit traffic over network links, including disposing transmission units into flows; grouping flows into first flow lists, each corresponding to a selected network link; determining a traffic metric representative of a traffic load on the selected network link; responsive to the traffic metric, regrouping flows into second flow lists corresponding to the selected network link, the regrouping balancing the transmission unit traffic among the network links; and transmitting the respective second flow list over the respective selected network link.

Abstract: A node comprises at least an interconnect, one or more coherent agents coupled to the interconnect, and a memory bridge coupled to the interconnect. The memory bridge is configured to maintain coherency on the interconnect on behalf of other nodes. In one embodiment, the interconnect does not permit retry of a transaction initiated thereon, and the memory bridge is configured to provide a response during a response phase of the transaction based on a state of a coherency block accessed by the transaction in the other nodes. In another embodiment, the node further comprises a plurality of interface circuits and a switch. Each of the plurality of interface circuits is configured to couple to an interface to receive coherency commands from other nodes. The switch is configured to selectively couple the plurality of interface circuits to the memory bridge to transmit the coherency commands to the memory bridge.