Abstract: A method and apparatus is disclosed for detecting the amount of unknown offset present in a received data stream. The unknown phase offset may offset the phase of the transmitted data stream from the received data stream. A phase detector uses a soft-decision slicer to estimate the content of a modulation transmitted data stream. The soft-decision slicer generates an estimate of the transmitted data stream depending on the location of the received data stream in relation to a transfer function of the soft-decision slicer depending on the modulation scheme of the received data stream. The phase detector uses the estimate of the transmitted data stream to calculate the amount of the unknown phase offset.

Abstract: A system and method allow for safe use of headphones that include a microphone when using the headphones with a cellular phone, a music device, or the like. A desired audio signal, e.g., a voice of a caller or music, is discontinued when a microphone associated with the headphones picks up either a change in ambient noise or a particular type of ambient noise, e.g., an ambulance, a police car, a fire truck, someone yelling, brakes squealing, or the like. During this state, the headphones output either an audible alert signal, the ambient noise, or a pre-stored signal that states “fire,” “police,”, “yelling,” etc. In this way, a person can safely talk on the phone or listen to music when walking or driving, while still being cognizant of what is going on around them.

Abstract: A system for processing wireless data packets allows for processing packets allows consolidation of security processing. Security processing is performed in accordance with multiple security policies. This processing is done in a single front end processing block. Different security processes can be performed in parallel. Processing overhead is reduced by eliminating the need to redundantly check packet characteristics to assess the different security requirements imposed by security policies. Further, the present invention also substantially reduces the CPU cycles required to transport data back and forth from memory to a cryptographic coprocessor.

Abstract: The present invention provides systems, methods, and computer program products for performing fractional B-spline interpolation. The fractional B-spline interpolation system includes an upsampling module and a fractional B-spline interpolation filter. The B-spline interpolation filter calculates a set of B-spline interpolation coefficients at a plurality of fine index points using the second derivative of the B-spline base function. The number of B-spline interpolation coefficients in the set is equal to the number of polynomial segments comprising the B-spline base function. For each fine index point, each coefficient in a set of B-spline interpolation coefficients is multiplied by a corresponding original sampling point to generate the value of the interpolated signal at the fine index point. The B-spline interpolation filter also includes a memory for storing a set of initial values needed by the B-spline interpolation filter to calculate the B-spline interpolation coefficients.

Abstract: A method and system for creating an ethernet-formatted packet from an upstream DOCSIS packet. The upstream packet is first received along with packet characteristic data that is contained in physical layer prepend data and in the packet header. A packet tag is then created, based on the packet characteristic data. The packet characteristic data includes identifiers for the transmitting remote device and the channel over which the transmission is sent. Packet characteristic data also includes information about the physical characteristics of the transmission signal, such as the power level and time offset. The packet characteristic data also includes administrative information, such as the minislot count at which the packet is received and whether the packet was received in contention. The packet tag is appended to the payload of the upstream packet. Also appended to the payload is an encapsulation tag, and source and destination address headers. The result is a packet in an ethernet format.

Abstract: An integrated frequency-shift keying (FSK) transceiver fabricated on an integrated circuit (IC) chip. The integrated FSK transceiver provides a bidirectional exchange of information between a satellite set-top box converter or modem and one or more outdoor units (ODUs). The integrated FSK transceiver includes a binary FSK receiver coupled to one or more translation modules of associated satellite antennas. The FSK receiver provides management information transmitted from the translation modules to a baseband interface. The baseband interface provides connectivity between the translation modules and the satellite converter set-top box and/or data modem. A binary FSK transmitter transmits management information generated by the baseband interface to the translation modules.

Abstract: A system for performing a computationally efficient method of searching through N Vector Quantization (VQ) codevectors for a preferred one of the N VQ codevectors predicts a speech signal to derive a residual signal, derives a ZERO-INPUT response error vector common to each of the N VQ codevectors, derives N ZERO-STATE response error vectors each based on a corresponding one of the N VQ codevectors, and selects the preferred one of the N VQ codevectors based on the N ZERO-STATE response error vectors and the ZERO-INPUT response error vector.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: A differential comparator with reduced offset. The differential comparator includes a first transistor coupled to a first input current and a second transistor coupled to a second input current. The first and second transistors are biased as diodes during a reset phase to store an offset voltage on parasitic capacitances of the first and second transistors. The first and second transistors are connected together as a latch to provide an output during a latch phase. Drain currents of the first and the second transistors substantially equal the first and the second input currents, respectively, during the reset phase and at the beginning of the latch phase. During the latch phase, currents approximately twice as large as differential-mode signal currents provided by the first and the second input currents are provided to the first and the second transistors, respectively.

Abstract: Symbol by symbol variable constellation type and/or mapping capable communication device. A communication device is operable to perform processing of a variable constellation signal whose constellation varies on a symbol by symbol basis. This may involve performing encoding of input to generate the variable constellation signal; alternatively or in addition to, this may involve performing decoding of a variable constellation signal as well. In doing so, this approach may involve using a single encoder and/or decoder (depending on the application). In some instances, a single device is operable to encode a first variable constellation signal (for transmission to another device) and to decode a second variable constellation signal (that has been received from another device). In addition, a method of coding (including one or both of encoding and decoding) may also operate of a variable constellation signal whose constellation varies on a symbol by symbol basis.

Abstract: A low-speed DLL facilitates a deskewed interface between a high-speed RX data demultiplexer circuit directly to an Application Specific Integrated Circuit (ASIC) with which it is integrated by locking a 156 MHz ASIC clock to a 156 MHz reference derived from a high speed 2.5 GHz clock. The DLL employs a digital interpolator to generate 32 phases of the 156 MHz clock. The digital interpolator supplies the phases using a double clocked shift register with recirculating feedback. The shift register is double clocked using the 2.5 GHz clock. The register outputs are tapped and fed to a 32:1 multiplexer having a phase select input that is controlled by the phase difference signal generated by the DLL. The phase difference control signal is converted to a digital representation of its magnitude by which the requisite number of phase shift increments may be selected.

Abstract: An integrated RF front-end architecture is disclosed. Such an integrated RF front-end architecture includes a multi-tap balun, a low noise amplifier and a power amplifier core. The multi-tap balun includes a single-ended primary winding and a symmetrical multi-tap secondary winding, wherein the single-ended primary winding is operably coupled to an antenna. The low noise amplifier is coupled to a first set of taps of the symmetrical multi-tap secondary winding. The power amplifier core is coupled to a second set of taps of the symmetrical multi-tap secondary winding and can be a two stage amplifier having a driver stage and an output stage. The multi-tap balun, low noise amplifier and power amplifier core can be on-chip components or can be fabricated to be discrete components on a printed circuit board.

Abstract: A circuit for protection of a transceiver input includes an input transistor and a first resistor connected between the drain of the input transistor and an input node. A plurality of reverse-biased diodes connected between a supply voltage and the input node. An output node is connected to the source of the input transistor. A first forward-biased diode connected between the power supply and the plurality of reverse-biased transistors. A second forward-biased diode and a second resistor are connected between the first forward biased transistor and the gate of the input transistor. A pre-driver circuit includes first and second transistors forming a differential pair and driven by a differential input voltage. A third transistor is connected between sources of the first and second transistors and ground. First and second resistors are connected to drains of the first and second transistors, respectively. A fourth transistor is connected between a power supply voltage and the first and second resistors.

Abstract: Systems and methods for pulse stretching architectures for phase alignment of multi-frequency clocks for high speed data acquisitions are disclosed. A high speed data acquisition system includes a transmitter and a receiver. The receiver includes a multi-frequency clock generator that generates a plurality of clock signals, a pattern check module that detects a test pattern received from the transmitter and outputs a stretch command signal, and a stretch pulse generator that receives the stretch command signal and provides a stretch pulse signal that aligns the phases of the plurality of clock signals generated by the multi-frequency clock generator. Methods for initializing and shifting multi-phase clock signals to optimize error performance of a high speed data acquisition system are also provided.

Abstract: A connection assembly provides an electrical connection from a coaxial cable to planar circuitry. The connection assembly includes an innermost connector node, configured to connect electrically to an innermost conductor of a coaxial cable, having one opening that allows for the innermost conductor to pass through the one opening and having a first contact extending perpendicular to a center line of the coaxial cable, a braided connector node, configured to connect electrically to a braided conductor of the coaxial cable, having two openings that allow for portions of the coaxial cable to pass through the two openings and having a second contact extending perpendicular to the center line of the coaxial cable and a connection module, connected to the innermost connector node and the braided connector node and configured to maintain an orientation of the innermost and braided connector nodes and the first and second contacts.

Abstract: A fuse corner pad is part of an integrated circuit that includes a built-in fuse contact and a plurality of auxiliary pads. The fuse contact is a conductive metallic or metalloid structure that is connected to a fuse element. The fuse contact and fuse element are used inside of the fuse corner pad for programmability (e.g., for security) and/or adjustment (e.g., trimming) of analog and/or digital signals. The fuse contact and fuse element are not required to be bonded to an external electrical connection (such as, a pin or ball). The auxiliary pads provide a variety of functional or non-functional applications, such as testing, probing, programming, and/or circuit adjustment.

Abstract: A frequency translation apparatus provides selective frequency translation of an input signal with reduced distortion effects. The frequency translation apparatus includes a plurality of mixers. Each mixer is coupled to the input signal and to a corresponding local oscillator (LO) signal. The frequency translation apparatus further includes a plurality of bias networks corresponding to the plurality of mixers. Each bias network produces a bias voltage for a corresponding mixer. A mixer is deactivated by providing an LO input of a mixer to a corresponding bias voltage. A mixer is activated by not providing the LO input of the mixer to the corresponding bias voltage. An activated mixer subsequently frequency translates the input signal according to the corresponding LO signal to produce a corresponding output signal.

Abstract: A baseband controller system creates and maintains a schedule of synchronized events and reviews the schedule as a part of determining whether to initiate a transmission of a non-synchronous event (one that is not time sensitive, for example, e-mail). One aspect of the present invention is to create a system and method that avoids a possibility of collision between synchronized and non-synchronized communication events. A synchronized event is a scheduled transmission of time sensitive data such as what is often known as continuous bit rate data. Examples include video and voice wherein a collision (inability to transmit the continuous bit rate data) may result in degradation of signal quality at the receiving end. The inventive system and method evaluate the schedule of synchronized events in relation to the present time and determine whether a non-synchronized event may be transmitted without the likelihood of a collision.

Abstract: A baseband controller includes a microsequencer with special hardware resources circuitry and a configuration that supports real-time Bluetooth functionality for an upper limit of Bluetooth slave devices. The microsequencer includes a 72-bit correlator that may also be used as an accumulator, wherein the topology provides that the correlator can communicate with a 72-bit arithmetic logic unit that correspondingly enables the correlator to act as an accumulator. The microsequencer also includes a plurality of clocks and timers for facilitating Bluetooth timing functionality, and at least four registers for temporarily storing computational data, where each of the storage registers have different sizes for accommodating different-sized packets of computational data.

Abstract: A number of features for enhancing the performance of a wireless communication system, in which data is transmitted between a central node and a plurality of subscriber nodes located remotely with respect to the central node, are presented. The power transmission level, slot timing, and equalization of the subscriber nodes are set by a ranging process. Data is transmitted by the subscriber nodes in fragmented form. Various measures are taken to make transmission from the subscriber nodes robust. The uplink data transmission is controlled to permit multiple access from the subscriber nodes.