Abstract: A system and method for guaranteeing a delay jitter bound when scheduling bandwidth grants for voice calls via a communication medium is provided. The method includes the steps of: determining the delay jitter bound; based on the determined delay jitter bound, dividing a packetization frame period into phases; assigning a voice call to one of the phases; and scheduling a bandwidth grant to the voice call during the assigned phase, thereby guaranteeing the delay jitter bound. The system includes a scheduler, where the scheduler determines the delay jitter bound, divides a packetization frame period into phases based on the determined delay jitter bound, assigns a voice call to one of the phases, and schedules a bandwidth grant to the voice call during the assigned phase, thereby guaranteeing the delay jitter bound. A dejitter buffer implements a way to provide zero jitter service, even though the packet transmission on the cable network has jitter, by delaying the packet and thus converting jitter into delay.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A system and method for an improved analog front-end system is disclosed. By coupling a switch to the output of a track-and-hold circuit and to the input of a time-discrete circuit, such as an analog-to-digital converter, the time-discrete circuit can be disconnected from the track-and-hold circuit during the track mode of the track-and-hold circuit. This improved system reduces the load of the T/H circuit from the full input capacitance of the time-discrete circuit to the smaller parasitics of the switch thereby providing a T/H circuit with lower power consumption and smaller area while maintaining high speed and high accuracy.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: Systems and methods are disclosed for reducing or eliminating hot carrier injection stress in circuits. In one embodiment, the present invention relates to an integrated circuit comprising an IO PAD, an output circuit coupled to at least the IO PAD and a stress circuit. The stress circuit is coupled to at least the output circuit and is adapted to limit a high voltage across the output circuit when the output circuit is enabled, thereby reducing stress on the output circuit. In one embodiment, the stress circuit comprises at least one transistor device (a p-channel device or two stacked p-channel devices, for example) and the output circuit comprises a transistor device (an n-channel device or two stacked n-channel devices).

Abstract: The invention enables an increase in linear power output ranges in a power amplifier by using an unmatched power amplifier driver in place of a matched power amplifier driver.

Abstract: A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second dimension, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the row and column of the cell in the array; and a processing unit capable of executing instructions that operate on a plurality of memory cells in the register, the instructions identifying the plurality of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell; the data processor being arranged to interpret a first form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first grou

Abstract: A power management scheme for a wireless communications device substantially implemented on a single CMOS integrated circuit is described. The present invention provides a method and apparatus for generating first and second clock signals for a wireless communication device, with the first and second clock signals corresponding first and second power levels, depending on the operating mode of the wireless communication unit. In the first operating state, the transceiver in the RF analog module is operational and the clock generator provides a first clock signal having the high-speed, high-accuracy characteristics necessary to maintain efficient operation of the transceiver. In a second operating state, the transceiver in the RF analog module is turned off. In this second operational state, the clock generator provides a second clock signal having a frequency and quality sufficient to maintain efficient operation of the digital modules in the wireless communication device.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A Radio Frequency (RF) power amplifier includes a transconductance stage, an AC coupling element, and a cascode stage. The transconductance stage is adapted to receive an input RF voltage signal and to produce an output RF current signal. The cascode stage is adapted to receive an input RF current signal and to produce an output RF voltage signal. The AC coupling element couples between the transconductance stage and the cascode stage and is operable to AC couple the output RF current signal of the transconductance stage as the input RF current signal of the cascode stage.

Abstract: A semiconductor device exhibiting low parasitic resistance comprises a first substrate characterized by a first resistivity; a second substrate characterized by a second resistivity, a third substrate and a metal element. These substrates form a multi-layer semiconductor device where the second substrate is formed on the first substrate; the third substrate is formed on the second substrate; and the metal element is formed on the third substrate. The second substrate is electrically grounded and is highly doped with acceptor dopant as compared to the first substrate. In this way, the second resistivity is lower than the first resistivity.

Abstract: A multi-level power amplifier architecture using a multi-tap transformer implemented on a single CMOS integrated circuit wireless communications device is described. By providing a multi-tap transformer for coupling a plurality of power amplifiers to a shared output impedance, such as an antenna, power transmission may be made at different levels while maintaining efficiency. With a multi-tap transformer having “N” taps featuring “N” different impedance levels, each tap may be connected to an amplifier cell which delivers power into the transformer at the tap for coupling to the output load. Any one of the “N” amplifier cells can be turned on at once along with any combination of the “N” amplifier cells.

Abstract: A telephony system and method is provided that reduces delay and provides better utilization of upstream bandwidth in delivering packet telephony services to a plurality of subscriber lines via a cable modem system. An exemplary system includes a plurality of voice processing modules, a host processor, and a buffer. Each voice processing module receives digital voice signals from a separate set of subscriber lines, compresses the digital voice signals to generate a voice packet, and transfers the voice packet to the buffer. The host processor then assembles a packet by concatenating the voice packets and transmits the assembled packet for delivery over a data network. Because the plurality of voice processing modules process the voice packets in parallel, delay is reduced in the assembly and transmission of the assembled packet.

Abstract: A Class AB voltage-to-current converter includes a plurality of DC coupled transconductance stages that produce a linearized output and a biasing circuit. The biasing circuit generates a primary bias voltage that is greater than a generated secondary bias voltage. As such, the first transconductance stage becomes active before the second transconductance stage with respect to the magnitude of a differential input voltage, thereby allowing the transconductance of the secondary transconductance stage to be added (or subtracted) from the transconductance of the primary stage to improve the overall transconductance of the Class AB voltage-to-current converter. As each of the plurality of transconductance stages is biased differently from the others, the various transconductance stages are biased on to differing amounts based upon the biasing signals as well as the input signal.

Abstract: The present invention provides a method for use with program overlays, wherein code segments, along with data segments pertaining to the code segments, are transferred into a receiving memory segment. Program code is separated into common code and overlay code. The overlay code is then broken down into segments according to functionality, and the need to create segments that will fit into a receiving memory segment. An overlay control file is created for each segment, then a wrapper file. Linker command files are created for the common area and code area. The wrapper files and linker command files are used to create a common image file for the code/data. The common image is used to produce overlay sections, which are then concatenated together into one file. This one file is then loaded into memory for transfer of the overlays to a receiving memory area.

Abstract: A multi-modulus divider for high speed applications is provided and may comprise a multistage divider generating a divided signal from an output portion of a divider module for a current stage. The divided signal may be fed back to an input portion of the divider module in the current stage via a reduced feedback delay path. If the input portion of the divider module in the current stage is coupled to the divider module in a previous stage, a first load signal may be communicated from the divider module in the current stage to the divider module in the previous stage. If the divider module in the current stage is coupled to the divider module in the previous stage, the method may further comprise receiving the divided signal from the divider module in the previous stage.

Abstract: In an RF communication system, aspects of a method for a temperature sensor for transmitter output power compensation may comprise generating an output voltage, which may vary with temperature, from at least one reference voltage, wherein at least one reference voltage may vary proportionally with temperature. The output voltage may be converted to a digital value. The reference voltage may be generated by utilizing a current source to generate a voltage across a resistive load. A control voltage generated from an operational amplifier may control at least one current source. PN junction characteristics of at least one bipolar junction transistor may be utilized to generate an input reference voltage for the operational amplifier. Resistance of at least one resistor, which may be coupled to the bipolar junction transistor and to the operational amplifier, may be adjusted to determine a current level from the current source at a plurality of different temperatures.

Abstract: Systems and methods are disclosed for to compensating reference frequency drift in a communications system having a plurality of modems and a headend, where the system requires critical upstream timing. One embodiment of the method includes learning or determining the relative delay of each modem and reporting each modem's unique delay (relative to the closest modem) to the headend. The method further includes the headend monitoring its own reference for frequency drift, the modem broadcasting pertinent frequency drift information to the modems and adjusting the modems' upstream timing to account for each modem's unique distance (i.e., delay) combined with the broadcast stream of frequency drift information.

Abstract: A downstream adaptive modulation system and method. The downstream adaptive modulation system comprises a wireless access termination system and one or more wireless modems. The wireless access termination system includes a plurality of queues and a parser. The parser parses data traffic onto the plurality of queues. Each queue is associated with a different coding and modulation scheme. Each of the one or more wireless modems receives data traffic from the plurality of queues based on the wireless modem's ability to demodulate and decode the signal from each of the plurality of queues. When a wireless modem experiences a change in signal strength, the present invention enables the wireless modem to adapt to data from other queues to compensate for the change in signal strength. Thus, if the signal strength improves over a period of time, the wireless modem may receive data at a higher order modulation and FEC code rate.

Abstract: A method for forming a non-iterative time-domain equalizer (TEQ) and apparatus corresponding thereto. A channel response H(z) is followed by a TEQ response A(z) and a residual output B(z) is chosen so that its degree is less than a cyclic prefix. An error signal is formed so that E(z)=H(z)A(z)?B(z). With a unit input, the error signal is set to zero and B(z)=H(z)A(z). Each signal is expressed as a polynomial, having varying degrees, and a having corresponding coefficients. Once expanded, the coefficients of similar degree can be equated on both sides of the equation. The error signal can then be determined in terms of coefficients corresponding to the TEQ and the residual signal. The coefficients of the channel response can be derived from the channel training estimates. The error signal is minimized and the result is solved for in terms of the desired TEQ coefficients.