Abstract: Successive interference canceling for CMDA. ICI may result from a signal's multipath effects, or by filtering/suppression of some of the component energy of the signaling waveforms. Energy component attenuation destroys orthogonality of CDMA symbols thereby causing ICI. An ICF suppresses frequency domain portions (attenuates ingress), but also introduces ICI. Following the ICF, the signal is de-spread, sliced, re-spread and convolved with the ICF echoes (except first tap echoes). Convolving re-spread hard decisions with delayed ICF taps is equivalent to partially re-modulating the first-pass hard decisions to efficiently “add-back-in” the signal energy which was blanked/subtracted by the ICF. Alternatively, parameter estimation de-rotates and re-rotates soft symbols and hard decisions, respectively, compensating for undesirable symbol rotation. The convolved signal is subtracted from a delayed version of the ICF output signal.

Abstract: Systems and methods that enable high quality audio teleconferencing are disclosed. In one embodiment of the present invention, a signal processor receives signals from a spatially dispersed set of directional microphones, processing the microphone signals and the far-end received audio into a signal for transmission to a far-end party. The processing may comprise the use of one or more algorithms that reduce conference room noise and may selectively increase participant audio levels by processing the microphone signals using beamforming techniques. An embodiment of the present invention may also comprise one or more omni-directional microphones that may be used in cooperation with the directional microphones to adjust for background noise, acoustic echo, and the existence of side conversations.

Abstract: A method and system for conditionally carrying out an operation defined in a computer instruction wherein a computer instruction is implemented on so-called packed operands; that is, operands containing a plurality of packed objects in respective lanes. An operation defined in the computer instruction is conditionally carried out in dependence on stored condition values which determine for each lane whether or not the operation is to be executed on objects in that lane.

Abstract: Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.

Abstract: An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

Abstract: An extended range variable gain amplifier is described. The variable gain capability is achieved by replacing differential pair amplifiers having an input signal with less attenuation with one having an input signal that is more attenuated. This replacement continues until only ten differential pair amplifiers are remaining. At this point, if less gain is desired, differential pair amplifiers are turned off, but are not replaced. A minimum number of amplifiers will remain on.

Abstract: Methods and apparatus are provided for sequencing data in a cryptography accelerator with multiple cryptographic processing cores. Cryptographic processing cores are grouped into blocks of cryptographic processing cores to efficiently process received data. Mechanisms are provided to order data sequences at both the cryptographic processing core block level and the cryptographic processing core level.

Abstract: An impairment compensation sequence for use in a communications system susceptible to one or more potential impairments each periodic in an integer number of symbols includes N phases, wherein N is selected such that each potential impairment, if present, is periodic therein, and a sequence of symbols, the sequence organized to place at least one instance of each symbol from a predetermined set of symbols in each phase to allow detection of the potential impairments in each of the N phases. The potential impairments may include robbed-bit signaling and padding. Using estimates prepared based on such an impairment compensation sequence, individual phase intervals may be grouped according to similarity of apparent aggregate effect of the impairments thereon without identification of individual impairments active in the particular phases. Constellation points may then be assigned based on group characteristics corresponding to phase intervals.

Abstract: Method and apparatus for recovering a clock and data from a data signal. One method of the invention includes receiving the data signal having a first data rate and receiving a clock signal having a first clock frequency, and alternating between a first level and a second level. The data signal is stored when the clock signal alternates from the first level to the second level, and the stored data signal is provided as a first signal a first amount of time later. The first signal is stored when the clock signal alternates from the first level to the second level, and the stored first signal is provided as a second signal a second amount of time later. A third signal is provided by delaying the first signal for a third amount of time. The third signal is stored when the clock signal alternates from the second level to the first level, and the stored third signal is provided as a fourth signal a fourth amount of time later. A fifth signal is provided by delaying the data signal a fifth amount of time.

Abstract: A system, method, and computer product for high-speed multiplication of binary numbers. A multiplier X is first encoded, and the encoded multiplier is then used in a multiplication process that yields the product. The encoding is performed in a manner that allows the actual multiplication process to proceed quickly. X is copied into a variable Z. Z is then manipulated to form the coded version of the multiplier. The bits of the multiplier X are read two at a time, starting with the least significant two bits. If the bit pair Xi+1Xi is equal to 11, then 1 is added to Zi+2. The process continues for successive non-overlapping pairs of bits, until the most significant three bits of X are reached. These last three bits are encoded using a table look-up process.

Abstract: A method for communicating information is disclosed wherein a time slot is allocated in a time division multiple access system for a transmission from a subscriber to a headend. Synchronization of a clock of the subscriber with respect to a clock of the headend is enhanced using a message transmitted from the headend to the subscriber which is indicative of an error in a subscriber transmission time with respect to the time slot. A feedback loop process is used to determine at least one of fractional symbol timing correction and carrier phase correction of a transmission from the subscriber to the headend. Filter coefficients are generated at the headend from a ranging signal transmitted from the subscriber to the headend and transmitting the filter coefficients from the headend to the subscriber, the filter coefficients being used by the subscriber to compensate for noise in a transmission from the subscriber to the headend.

Abstract: In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock.

Abstract: An apparatus for processing a received signal includes an analog-to-digital converter (ADC) configured to produce a sampled signal from a received signal using a candidate sampling phase. An adaptive filter includes adaptive filter coefficients and is configured to receive the sampled signal and converge the filter coefficients based on the candidate sampling phase. A controller includes a module for comparing the converged filter coefficients to filter coefficient thresholds, and a module for determining a largest filter coefficient among one or more excessive filter coefficients that exceed one or more corresponding filter coefficient thresholds. The apparatus is stepped through multiple candidate sampling phases. A best sampling phase is selected based on the largest filter coefficients associated with the candidate sampling phases.

Abstract: Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.

Abstract: Iterative data-aided carrier CFO estimation for CDMA systems. Any communication receiver may be adapted to perform the iterative data-aided carrier CFO estimation. The iterative data-aided carrier CFO estimation is performed using a high accuracy method. The operation may be described as follows: a received signal is despread and buffered. Using the received preamble sequence, an initial estimate of the CFO is obtained. This estimate is used to correct the whole despread data. The corrected data using the initial CFO estimate is sliced. Each despread data symbol is divided by the corresponding sliced data decision. The obtained sequence is then averaged across different codes to obtain a less noisy sequence, which is then used to estimate the CFO again. The procedure can be repeated (iterated) to obtain a more accurate carrier frequency offset estimate; the number of times in which the procedure is repeated may be programmable or predetermined.

Abstract: A Multi-tone transmission system processes input data through a plurality of intermediate processing stages 12, 14, 16 and corresponding stages of intermediate data 18,20. A symbol including a number of tones is obtained therefrom by an inverse Fourier transform 24 and stored in a buffer 158. The peak amplitude that the symbol would contain after the subsequent processing in the analogue front end 146 is modelled and compared with a threshold. If the modelled peak amplitude in the symbol exceeds the threshold, the symbol stored in the buffer 158 is regenerated. The symbols stored in the buffer are output through the analogue front end 146.

Abstract: Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

Abstract: A Radio Frequency (RF) device includes a semi conductive die and a package in which the semi conductive die mounts. The semi conductive die includes a first portion of an RF circuit and a plurality of die pads formed thereon. The package includes a heat slug upon which the semi conductive die resides, a plurality of package pins, a plurality of bond wires, a downbond rail, and a plurality of downbonds. Each of the bond wires couples between a corresponding die pad and a corresponding package pin. The downbond rail couples to the heat slug. At least one downbond couples between a die pad corresponding to the first portion of the RF circuit and a respective location on the downbond rail, serves as an inductor for a second portion of the RF circuit, may include a plurality of downbonds coupled in parallel, and has a length and/or a diameter selected to provide a desired inductance.

Abstract: There is disclosed a technique in which any peaks above a threshold level are reduced, but not clipped, such that the effects of such peaks is reduced. Although the implementation of the technique preferably includes a clipping step, it is performed on the front-end rather than as the last step in the technique, such that the output signal is not a clipped signal. Any noise introduced by the clipping step, so-called clipping noise, is preferably filtered out of the useful frequency band of the signal.

Abstract: An electronic structure having a first conductive layer provided by a dual damascene fabrication process; an etch-stop layer provided by the fabrication process, and electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The structure can be, for example, a metal-insulator-metal capacitor, an antifuse, and the like.