Abstract: A low noise amplifier (LNA), which utilizes an AC coupling technique that can internally bias diodes in such a way as to provide effective low noise amplification, is provided. The low noise amplifier includes an input to an amplifier circuit, and an AC coupling capacitor disposed externally to a chip boundary of the amplifier circuit.

Abstract: A method for controlling transmit power of a radio frequency integrated circuit begins by sampling a continuous transmit signal strength indication (TSSI) for a predetermined number of sampling cycles to produce a plurality of TSSI samples. The process then proceeds to determine a normalized TSSI from the plurality of TSSI samples. The processing continues by converting the normalized TSSI into an estimated transmit power. The process continues by comparing the estimated transmit power with a desired transmit power. The processing then continues by determining a transmit power error based on the comparison of the estimated transmit power with the desired power. The process then continues by adjusting gain of a transmit section of the radio frequency integrated circuit based on the transmit power error such that the estimated transmit power substantially matches the desired transmit power.

Abstract: A processor is contemplated which includes a queue configured to store one or more instructions and a control circuit coupled to the queue. The control circuit is configured to detect a replay of a first instruction due to a dependency on a load miss. In response to detecting the replay, the control circuit is configured to inhibit issuance of the one or more instructions in the queue to one or more pipelines of the processor. A carrier medium comprising one or more data structures representing the processor are also contemplated, as are a method of detecting the replay and inhibiting issuance of instructions in the queue in response to detecting the replay.

Abstract: A printed circuit board includes two differential signal traces, a layer of core material, a layer of filler material, and a ground plane. The filler material is replaced by an air core under the differential signal traces.

Abstract: All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.

Abstract: A phase detector includes a first flip flop having a data input coupled to a first clock signal at a first frequency and a clock input coupled to a second clock signal at a second frequency. The frequency of the first clock signal is a multiple of the frequency of the second clock signal. The phase detector also includes a second flip flop having a data input coupled to an output of the first flip flop and a clock input coupled to the second clock signal.

Abstract: A gain boost circuit and methodology are described for providing improved gain boosting with tuned amplifier circuits, such as differential low noise amplifier circuits having output resonant tank circuits. By selectively controlling the current source for a negative transconductance stage coupled between the differential amplifier output and the output resonant tank circuits, the amplifier gain may be adjusted to compensate for temperature variations. In addition, the amplifier gain boost may be selectively added, removed or even incrementally adjusted by using a current source control circuit in the negative transconductance stage to adjust the negative transconductance value generated by the negative transconductance stage.

Abstract: A control terminal such as a CMTS is initialized to receive packets of voice calls having parameters including a bit rate, a packetization interval, and a call identification. A plurality of queues is created to define a corresponding plurality of phases at a sub-multiple of the packetization interval. Voice calls are admitted to the control terminal. The voice calls are distributed among the queues in a predetermined order as the voice calls are admitted and the voice calls removed from the queues as the voice calls are terminated. USGs are periodically issued at the phases defined by the queues. The USGs include a call identification and a grant of bandwidth sufficient to transmit the packets.

Abstract: RF communications received by a wireless terminal from a servicing base station are used to determine the channel quality such as reported bit error probability (BEP). The RF communications may be in the form of RF bursts that are part of a data frame. An estimated BEP may be determined from the signal to noise ratio (SNR) of the RF bursts and or a sequence of soft decisions extracted from the RF bursts, and their historical performance. The SNR maps to an estimated BEP based upon the modulation format of the RF bursts. The soft decisions decode to produce a data block. When the soft decisions decoded favorably, the re-encoded data block produces a sequence of re-encoded decisions. Comparing the re-encoded decisions to the soft decisions yields a re-encoded bit error (RBER). The reported BEP may be based upon the estimated BEP, RBER, and/or RBER threshold. The RBER threshold may be adaptively incremented or decremented depending upon whether or not the RF communications were properly decoded.

Abstract: A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second address of a second set of bytes contiguous to the first set. The least significant bits of the branch PC (those bits not included in the most significant bits of the addresses received by the circuit) are used to generate the least significant bits of the link/sequential address and to select one of the first address and the second address to supply the most significant bits.

Abstract: A local oscillation generator includes a clock circuit, a first divide module, a first mixing module, a second divide module, and a second mixing module. The clock circuit is operably coupled to generate a first clock signal. The first divide module is operably coupled to divide rate of the first clock signal by a first factor to produce a second clock signal. The first mixing module is operably coupled to mix the first clock signal and the second clock signal to produce a first local oscillation. The second divide module is operably coupled to divide rate of the second clock signal by a second factor to produce a third clock signal. The second mixing module is operably coupled to mix the first clock signal and the third clock signal to produce a second local oscillation.

Abstract: A balancing/unbalancing (balun) structure includes two input ports are coupled to a differential signal. An isolated port is connected to ground through a matched resistance. An output port is coupled to a single-ended signal corresponding to the differential signal. A plurality of traces connect the two input ports, the load connection port and a tap point to the output port. A f2 rejection filter is wrapped around the balun and includes a first folded element with a transmission length of ?2/4 and connected to the output port. A second folded element has a transmission length of ?2/4 and connected to the tap point. A third folded element connects the tap point to the output port and has a transmission length of ?2/4.

Abstract: A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.

Abstract: An Ethernet communication system device that switches between SGMII and GBIC modes of operation, without software intervention. For example, a physical layer device (“PHY”) for an Ethernet communication system that switches between SGMII and GBIC modes of operation, without software intervention, to match a link device mode of operation. The link device can be a Media Access Controller (“MAC”), a switch, an optical device, or the like. The PHY is coupled between the link device and a copper link media. The PHY can operate with a link device that has similar SGMII/GBIC switching capabilities. The PHY determines whether the link device is operating in SGMII or GBIC mode of operation. The link device mode of operation is then compared with a current PHY mode of operation. When the PHY mode of operation matches the link device mode of operation, the PHY continues to operate in the current PHY mode.

Abstract: An impairment compensation sequence for use in a communications system susceptible to one or more potential impairments each periodic in an integer number of symbols includes N phases, wherein N is selected such that each potential impairment, if present, is periodic therein, and a sequence of symbols, the sequence organized to place at least one instance of each symbol from a predetermined set of symbols in each phase to allow detection of the potential impairments in each of the N phases. The potential impairments may include robbed-bit signaling and padding. Using estimates prepared based on such an impairment compensation sequence, individual phase intervals may be grouped according to similarity of apparent aggregate effect of the impairments thereon without identification of individual impairments active in the particular phases. Constellation points may then be assigned based on group characteristics corresponding to phase intervals.

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a substantially planar first surface of a stiffener. The first surface of a substrate is attached to a substantially planar second surface of the stiffener. The second surface of the stiffener is opposed to the first surface of the stiffener. A centrally located protruding portion on the second surface of the stiffener is opposed to the centrally located cavity. The protruding portion extends through an opening in the substrate. A wire bond is coupled from a bond pad of the IC die to a contact pad on the first surface of the substrate through a through-pattern in the stiffener. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, a notch in an edge of the recessed portion, and a notch in an edge of the opening.

Abstract: A method and system for increasing the efficiency of providing bandwidth for voice traffic to a data provider via wireless communication mediums is provided. This is generally accomplished by not transmitting any data during the silence periods and playing out background noise (i.e., comfort noise) at the other end, to obtain significant bandwidth savings.

Abstract: Maximum likelihood detection of signals in a MIMO receiver. A system transformation is obtained by selecting a weighting matrix that when linearly transforming a channel utilized for wireless communication, results in a particular transformed triangular matrix. The weighting matrix is then used to provide a transformed vector for a received signal that allows a search in one constellation. In searching the constellation recursion values are used to calculate the Euclidean distances between set points of the constellation and the location on the constellation corresponding to the received signal for both bit values 0 and 1. Minimum Euclidean distances are determined for bit values 0 and 1 and the difference of the minimum Euclidean distances is used to compute the maximum likelihood value for bits contained in the received signal.

Abstract: A two way communication system is adapted for compatible inter-operation of a plurality of devices operating in accordance with a plurality of protocols. The communication system includes a first group of one or more remote devices that interface with a local host in accordance with a first protocol and a second group of one or more remote devices that interface with the local host in accordance with a second protocol. The local host includes a protocol processor that identifies transmissions from the first and second groups of remote devices and routes transmissions from the first group of remote devices to a first processor operating in accordance with the first protocol and also routes transmissions from the second group of remote devices to a second processor operating in accordance with the second protocol.

Abstract: A system and method for guaranteeing a delay jitter bound when scheduling bandwidth grants for voice calls via a communication medium is provided. The method includes the steps of: determining the delay jitter bound; based on the determined delay jitter bound, dividing a packetization frame period into phases; assigning a voice call to one of the phases; and scheduling a bandwidth grant to the voice call during the assigned phase, thereby guaranteeing the delay jitter bound. The system includes a scheduler, where the scheduler determines the delay jitter bound, divides a packetization frame period into phases based on the determined delay jitter bound, assigns a voice call to one of the phases, and schedules a bandwidth grant to the voice call during the assigned phase, thereby guaranteeing the delay jitter bound. A dejitter buffer implements a way to provide zero jitter service, even though the packet transmission on the cable network has jitter, by delaying the packet and thus converting jitter into delay.