Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: For each node, elapsed periodic time intervals are provided and counted since the transmission of a link integrity indication frame, a frame which can be received by all other nodes on the network and which contains a source identifier. Frames are received from a sending node and a node state status and a current received frame source address are maintained during each periodic time interval. Upon expiration of the periodic time interval, if the node state status is not indicative of network traffic and a count of the elapsed periodic time intervals since transmission of a link integrity indication frame is greater than a predefined count limit, a link integrity indication frame is transmitted.

Abstract: Methods and systems for processing signals are disclosed herein. In one aspect of the invention a circuit for processing signals may comprise a triple well (TW) NMOS transistor coupled to an amplifier core. The TW NMOS transistor may track process and temperature variations (PVT) of at least one NMOS transistor within the amplifier core. A drain of the TW NMOS transistor may be coupled to a first inductor and the first inductor may be coupled to a first voltage source. The first voltage source may generate a standard voltage of about 1.2V. A source of the TW NMOS transistor may be coupled to a second inductor and the second inductor may be coupled to the first voltage source. A gate of the TW NMOS transistor may be coupled to a second voltage source, where the second voltage source may generate a standard voltage of about 2.5V.

Abstract: An apparatus and method for a low voltage drop and thermally enhanced integrated circuit (IC) package are described. A substantially planar substrate having a plurality of contact pads on a first surface is electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate. An IC die having a first surface is mounted to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. A heat sink assembly is coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The heat sink assembly can also provide an electrical path from the IC die to the first surface of the substrate. The heat sink assembly may have one or two heat sink elements to provide thermal and/or electrical connectivity between the IC die and the substrate.

Abstract: A method for managing congestion in a stack of network switches includes the steps of receiving an incoming packet on a first port of a network switch for transmission to a destination port and determining if the destination port of the packet is a monitored port. Thereafter, the method determines a queue status of the destination port, if the destination port is determined to be a monitored port, and preschedules transmission of the incoming packet to the destination port if the destination port is determined to be a monitored port.

Abstract: Bandwidth efficient coded modulation scheme based on MLC (Multi-Level Code) signals having multiple maps. The use of multiple maps is adapted to various types of coded signals including multi-level LDPC coded modulation signals and other MLC signals to provide for a significant performance gain in the continual effort trying to reach towards Shannon's limit. In the instance of LDPC coded signals, various level LDPC codewords are generated from individual corresponding LDPC encoders. These various level LDPC codewords are arranged into a number of sub-blocks. Encoded bits from multiple level LDPC codewords within each of the sub-blocks are arranged to form symbols that are mapped according to at least two modulations. Each modulation includes a constellation shape and a corresponding mapping. This use of multiple mappings provides for improved performance when compared to encoders that employ only a single mapping.

Abstract: An improved method and apparatus for using common mode feedback to maintain a predetermined DC level for an intermediate frequency output signal. A common mode feedback capacitor-select switch module is operable to use a bandwidth control signal from a radio interface of a wireless device to selectively connect a plurality of common mode feedback capacitors to an operational amplifier, thereby generating a common mode feedback signal as an input to an active mixer conversion gain module. The predetermined combination of common mode feedback capacitors is used in combination with a plurality of bandwidth capacitors to generate an overall capacitance that maintains the bandwidth of the system at a predetermined value.

Abstract: A supervisory communications device, such as a base station within a wireless network, monitors and controls communications with a plurality of remote communications devices, such as mobile nodes, throughout a widely distributed network, including the Internet. The supervisory device establishes the upstream slot structure and allocates upstream bandwidth by sending messages over its downstream channel. The supervisory device also uses the messages and minislot counts to anticipate bursts from the remote devices. Dual registers are provided within the supervisory device to generate minislot counts. A primary register generates minislot counts for a current slot structure, and a secondary register generates minislot counts for a revised slot structure. Software executed on the supervisory device determines a switchover time for changing to the revised slot structure and revised minislot count.

Abstract: A transceiver device for processing a frame in a wireless local area network, where the frame is one of several frame formats, which include a high throughput frame format. The transceiver device receives a frame having a training sequence, a signal field and a data payload, and processes the training sequence to detect which signal field length of a plurality of signal field lengths was used in the received frame. With the signal field length, the device processes the signal field based upon the detected signal field length to retrieve the data payload processing information.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: An aspect of the of the invention may include the transfer of a block of data from a first memory location to a second memory location in a DRAM. During the transfer of the block of data from the first memory location, if an encryption mode is selected, the data may be buffered, encrypted, and then stored in the second memory location. If a decryption mode is selected, the transferred data may be buffered, decrypted and then stored in the second memory location. If a bypass mode is selected, the data may be buffered and then stored in the second memory location. In this regard, the encryption/decryption operations may be bypassed.

Abstract: A system includes an interface, a synchronization module, a pre-filtering module and a data alignment module. The interface is configured to connect a first device having a first transfer rate and a second device having a second transfer rate. The interface transfers a data stream from the first device to the second device. The synchronization module is provided within the second device and is configured to synchronize the first transfer rate and the second transfer rate. The pre-filtering module is connected to the synchronization module, and the pre-filtering module is configured to mask a non-compliant input within the data stream into a compliant output. The data alignment module is connected to the pre-filtering module, and the data alignment module is configured to perform logic computations on the legal output.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: A design for a differential amplifier with a large input common mode signal range. The differential amplifier comprises two differential pairs, each having two amplifying MOSFETs. A source follower is connected to the gate terminal of each amplifying MOSFET in one of the differential pairs. A differential signal applied to the differential amplifier comprises two separate signal. Each separate signal is applied to the gate terminals of both the amplifying MOSFET in the differential pair not driven by the source follower and the driven MOSFET of the source follower. The differential amplifier further comprises a pair of switch MOSFETs connected to a current source MOSFET. The switch MOSFETs act to control the distribution of the total current flowing from the current source MOSFET and, consequently, to determine which differential pair works dominantly to amplify the input signals.

Abstract: Presented herein is a line address computer for providing chroma coefficients to a chroma filter. At each horizontal synchronization pulse, the line address computer provides a set of interpolation weights to a chroma filter. The chroma filter uses the provided set of weights to interpolate pixels in chroma pixel positions in a display format from chroma pixels in another format.

Abstract: A system and method are used to provide uncorrelated code hopping in a communications system. A multi-bit linear shift register receives data and clocks the data fifteen times. A word assembler receives the shifted data and outputs a fifteen bit word. A mixer mixes the fifteen bit word with an numerical value of active codes to generate a mixed signal. A divider divides the mixed signal to produce a divided signal. A truncator truncates the divided signal to its seven most significant bits to produce a pseudo random hop number. A code matrix shifter circularly shifts the active codes in a code matrix based on the pseudo random hop number to produce a circularly shifted code. A transmitter transmits the circularly shifted code matrix.

Abstract: A method and computer program product for providing RTP suppression across a DOCSIS network. An index number and a set of rules are sent to a receiver. The index number indicates the type of header suppression technique (i.e., RTP header suppression) to be performed, and the set of rules define how to recreate the RTP packets on the receiving end. At least one complete RTP packet is transmitted upstream for enabling a receiver to learn the RTP header. Subsequent RTP packets are transmitted upstream for reconstruction at the receiving end. The subsequent RTP packets are comprised of delta values representing fields that dynamically change from packet to packet in an RTP header.

Abstract: A wireless network card includes an adaptable antenna connection structure that includes connections for one or more internal antennas and for one or more Radio Frequency (RF) connectors that may be coupled to one or more external antennas. A Printed Circuit Board (PCB) and electronic components located thereon form the wireless network card. The PCB includes a removable portion that, when removed, leaves an opening that receives an RF antenna connector. When the PCB is used to create a client wireless network card, one or more surface mount antennas are mounted on the PCB and coupled to surface mount antenna conductive pads formed thereon. The wireless network card may include (1) the surface mount antenna; (2) the RF connector; or (3) both the surface mount antenna and the RF connector.

Abstract: A receiver includes a filter stage that receives, filters, and equalizes a received signal, and a decisional feedback loop coupled to the filter stage that receives and processes a signal output from the filter stage using remodulation. The decisional feedback loop includes a converter that generates a baseband signal, a detector that generates a decision signal, a restorative signal generator that generates a restorative signal using remodulation, and a carrier loop that generates a frequency correction signal and provides a frequency-offset estimate. The restorative signal and the frequency correction signal are provided to the converter to compensate for inter-symbol interference. The presented “remodulation” technique decouples interaction between the carrier loop, the pre-filters, and the equalizer of the restorative signal generator, providing an architecture that is more stable and significantly faster than conventional architectures.

Abstract: A scheme for sharing antenna control pins in a wireless communications device implemented on a single CMOS integrated circuit is described. By providing a routing circuit for coupling the antenna control signal to the appropriate transceiver circuitry in a multi-transceiver system, antenna control signals may be efficiently processed using a minimum of pins on the wireless communication device.