Abstract: A communications network includes a management device and a remote device. The remote device includes a physical layer device (PHY) coupled to a link partner. An independent station manager of the remote device provides the bi-directional exchange of management information between the PHY and a serial-to-parallel (S/P) interface connecting the remote device and the management device. A station manager of the management device provides the bi-directional exchange of management information between the S/P interface and a Media Access Controller (MAC) of the management device. The independent station manager and the station manager transmit initiation messages, formatted according to a message template of an Auto-Negotiation (AN) routine of the S/P interface reserved for customization, to reserve an embedded management channel for the transfer of management information.

Abstract: Aspects of the invention may provide a method and system for adjusting a gain and/or a frequency response of an input signal for a multimode PHY device. A signal divider may apportion the input signal into a gain adjustment signal and/or an equalization adjustment signal upon receipt of the input signal. A signal adjuster coupled to the signal divider may adjust a gain of the apportioned gain adjustment signal within the multimode PHY device. An equalizer coupled to the signal divider may be configured to equalize the equalization adjustment signal within the multimode PHY device. A summer coupled to the equalizer and signal adjuster may be adapted to sum the adjusted adjustment signal and the equalized equalization adjustment signal within the multimode PHY device to create an output equalized signal having a desired gain and/or frequency response.

Abstract: An oscillator that provides a quadrature output and has a cross-coupled configuration is disclosed. The oscillator generates an output signal having a frequency. Two phase shift circuits, or stages, are activated by a control signal to provide phase shifts within the oscillator. Each phase shift circuit includes poles to provide the phase shift. A pole includes a varactor to tune, adjust or vary the phase shift accordingly.

Abstract: A CMOS gain stage includes biasing circuitry configured to insure saturation of a subsequent stage without a source follower circuit. The CMOS gain stage is optionally powered by a supply voltage that is greater than a permitted supply voltage for a processes technology that is used to fabricate the CMOS gain stage. In order to protect CMOS devices within the CMOS gain stage, optional drain-to-bulk junction punch-through protection circuitry is disclosed. A variety of optional features can be implemented alone and/or in various combinations of one another. Optional features include process-voltage-temperature (“PVT”) variation protection circuitry, which renders a gain relatively independent of process, voltage, and/or temperature variations. Optional features further include bandwidth enhancement circuitry.

Abstract: In a Noise Feedback Coding (NFC) system operable in a ZERO-STATE condition and a ZERO-INPUT condition, the NFC system including at least one filter having a filter memory, a method of updating the filter memory. The method comprises: (a) producing a ZERO-STATE contribution to the filter memory when the NFC system is in the ZERO-STATE condition; (b) producing a ZERO-INPUT contribution to the filter memory when the NFC system is in the ZERO-INPUT condition; and (c) updating the filter memory as a function of both the ZERO-STATE contribution and the ZERO-INPUT contribution.

Abstract: A power-down biasing circuit including a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first capacitor connected between the gate of the first NMOS transistor and ground. A plurality of NMOS transistors form a current multiplier and have gates connected to the current reference. A plurality of current mirrors are connected to drains of the plurality of NMOS transistors and to output switches.

Abstract: Methods and systems for reducing effects of digital loop dead zones add phase randomness to one or more asynchronous signals that are to be synchronized with a digital loop system clock. Phase randomness is added in one or more of a variety of ways including, without limitation, non-harmonic asynchronous signals and variable phase delay. The invention can be implemented in a variety of types of digital loops including, without limitation, phase locked loops (“PLLs”). For example, a PLL receives a system clock signal, a digital reference signal, and a feedback signal. The digital reference signal and/or the feedback signal is asynchronous with the system clock signal. A phase of the asynchronous signal(s) is randomized and then synchronized with the system clock signal, prior to phase difference detection. This reduces effects of digital loop dead zones that are otherwise introduced by synchronization.

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a clock and data recovery circuit and an output pre-emphasis circuit. The output pre-emphasis circuit controllably modifies the spectrum of the high-speed bit stream to pre-compensate for the spectral characteristics of a signal path upon which the high-speed bit stream will be output. In the RX path, pre-compensation is performed based upon the properties of the PCB and a servicing connector. In the TX path, pre-compensation is performed based upon the properties of a line side connector and a line side media.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A method to perform adaptive channel filtering on a Radio Frequency (RF) bursts in a cellular wireless communication system. This method first filters an input signal with a first stage filter having a first bandwidth to produce a first stage output signal. Then the first stage output signal is filtered with a second stage filter having a second bandwidth narrower than that of the first stage filter to produce a multi-stage output signal. A comparison between first stage performance measurements and multi-stage performance measurements determine the mode of operation of the adaptive multistage filter. A first mode of operation, selected when the first stage performance measurement compares favorably with the second stage performance measurement, selects the output of the first stage filter as the output of the multi-stage filter. Otherwise, a second mode of operation selects the output of the second stage filter as the output of the multi-stage filter.

Abstract: Improved apparatus for a radio communication system having a multiplicity of mobile transceiver units selectively in communication with a plurality of base transceiver units which communicate with one or two host computers for storage and manipulation of data collected by bar code scanners or other collection means associated with the mobile transceiver units. A network controller provides selective interface means to be employed between the host computers and the base transceivers whereby low data rate base transceivers may be utilized with the network controller while spread spectrum or high data rate networked base transceivers may be also utilized. The network controller may allow selection of interface means for three of its ports from its front panel with use of three input keys. The network controller is entirely external to the host computer or computers, and can couple to a variety of commonly encountered host ports.

Abstract: A method or apparatus for decoding of a BCH encoded signal begins by determining whether the received BCH encoded signal includes error. The decoding process continues when the received BCH encoded signal includes error by determining whether the error is correctable. This may be done by determining a number of errors of the received BCH encoded signal, identifying bit locations of the received BCH encoded signal having the error; counting the number of bit locations of the received BCH encoded signal having the error, comparing the number of errors to the number of bit locations of the received BCH encoded signal having the error, when the number of bit locations of the received BCH encoded signal having the error equals the number of errors, ceasing the identifying of the bit locations of the received BCH encoded signal having the error, and correcting information contained in the bit locations of the received BCH encoded signal having the error when the identifying of the bit locations is ceased.

Abstract: A system for adding a time stamp to transmission traffic on a network comprises a front end processor that receives a packet from the network and generates a Start Of Frame pulse and a LENGTH field corresponding to a length of the packet. A time stamp generator generates a time stamp by sampling the system master time counter. A synchronizer receives the SOF pulse and the LENGTH field from the front end processor, and generates a control signal. A multiplexer inputs the packet from the front end processor, the control signal and the time stamp, and outputs a modified packet with a field in the packet replaced by the time stamp.

Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA.

Abstract: An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

Abstract: An embedded processor system including at least one gated power unit including an internal ROM and a power controller that provides one or more gated power signals to selectively provide power to each gated power unit. The power controller provides a gated clock signal to the embedded processor to selectively control power consumption of the processor. The power controller powers down each gated power unit after freezing the processor and then powers up each gated power unit before reactivating the processor. The embedded processor system may include isolation circuitry, such as clamp circuitry or the like, that is operative to minimize current flow into each gated power unit when powered down. The gated power units may include a static function. The ROM of an embedded ROM-based microprocessor system is powered down when the microprocessor is idle to reduce or otherwise eliminate intrinsic leakage.

Abstract: Off-chip LC circuit for lowest ground and VDD impedance for power amplifier. A novel approach is made by which a chip to PCB (Printer Circuit Board) interface may be made such that the ground and VDD potential levels are effectively brought onto the die of the chip such that a true ground potential is maintained within the chip. This off-chip LC circuit operates cooperatively with an on-chip decoupling capacitor to reduce the overall effective inductance of the bond wires employed to bring signal and voltage levels from the die to the chip exterior. This circuit ensures a relatively low impedance for a PA (Power Amplifier) that is implemented within chip thereby providing for improved performance.

Abstract: A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, and an IR processing module. The baseband processor receives an analog signal corresponding to a data block and samples the analog signal to produce samples. The equalizer receives the samples from the baseband processor, equalizes the samples, and produces soft decision bits corresponding to the data block. The equalizer may be implemented as a distinct processing component or may be performed by the baseband processor or system processor. The system processor receives at least the soft decision bits and initiates IR operations. The IR processing module receives the soft decision bits of the data block and performs IR operations on the data block in an attempt to correctly decode a corresponding data block.

Abstract: The present invention finds the optimum organization of compiled code within an application to ensure maximal cache efficiency. A configuration file specifies predefined cache, optimization, and application parameters. The cache parameters include a cache size, cache line size, set associativity, address-to-cache-line mapping algorithm, and set replacement algorithm. The optimization parameters specify the minimum acceptable efficiency level. The application parameters include a list of object modules and functions within those modules. All possible orderings of the modules are stepped through to determine where the specified functions fall within the cache given the location of the function within the module. The function locations in each permutation of the orderings are analyzed to find a solution that matches or beats the optimization parameters. In an embodiment, a front-end analysis program (“tool”) and a back-end processing stage, usually related to a linker, are provided.

Abstract: A wireless interface device services communications between a wirelessly enabled host and at least one user input device. The wireless interface device includes a wireless interface unit, a processing unit, an input/output unit, and may include a power management unit. The wireless interface unit wirelessly interfaces with the wirelessly enabled host. The processing unit and the wireless interface unit interact to determine when the wireless interface unit has established a link with the wirelessly enabled host. When the wireless interface unit has established a link with the wirelessly enabled host, the processing unit interacts with the input/output unit to direct the input/output unit to output a link established indication. When the wireless interface unit enters a sniff mode or a park mode, a second link established indication may be provided. When the link is taken down or lost, a link non-established indication may be provided.