Abstract: Methods and systems for reconfigurable soft-output bit demapping, reconfigurable for different modes of operation (i.e., different transmitter/receiver configurations) and for different modulation schemes are provided. In an embodiment, a reconfigurable soft-output bit demapping system includes a mode/modulation independent equalizer, a plurality of mode/modulation independent soft-slicers coupled to the outputs of the equalizer, a plurality of mode/modulation independent post-scalers coupled to the outputs of the soft-slicers, and a mode-dependent coefficient calculator. The coefficient calculator generates parameters for configuring the equalizer, the soft-slicers, and the post-scalers according to the used mode of operation and modulation scheme.

Abstract: A number of features for enhancing the performance of a communication system, in which data is transmitted between a base station and a plurality of subscriber stations located different distances from the base station, are presented. The power transmission level, slot timing, and equalization of the subscriber stations are set by a ranging process. Data is transmitted by the subscriber stations in fragmented form. Various measures are taken to make transmission from the subscriber stations robust. The uplink data transmission is controlled to permit multiple access from the subscriber stations.

Abstract: A downstream adaptive modulation system and method. The downstream adaptive modulation system comprises a wireless access termination system and one or more wireless modems. The wireless access termination system includes a plurality of queues and a parser. The parser parses data traffic onto the plurality of queues. Each queue is associated with a different coding and modulation scheme. Each of the one or more wireless modems receives data traffic from the plurality of queues based on the wireless modem's ability to demodulate and decode the signal from each of the plurality of queues. When a wireless modem experiences a change in signal strength, the present invention enables the wireless modem to adapt to data from other queues to compensate for the change in signal strength. Thus, if the signal strength improves over a period of time, the wireless modem may receive data at a higher order modulation and FEC code rate.

Abstract: A method for collision avoidance in multiple protocol networks using a shared communication medium begins by determining a first protocol probable active time period. The method continues by determining a first protocol probable inactive time period. The method continues by generating a transmit blocking indication based on the first protocol probable active time period and the first protocol probable inactive time period.

Abstract: A method, system and computer program product for a generic data storage interface for local and remote networked storage is provided. It comprises providing a data storage interface accessible by an operating system, transmitting data from an application running on the operating system to the data storage interface and selectively storing the data using the same data storage interface in either a local or a remote networked storage location.

Abstract: A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one redundant predecoder adapted to be shifted in for at least one active predecoder of a plurality of predecoders adapted to be shifted out.

Abstract: A method is described for correcting sampling frequency offset (SFO) of a data packet in a communications system where carrier frequency (fc) and sampling frequency (fs) are driven by a common clock source. The method comprises, for each lth symbol in the data packet, estimating carrier frequency offset (CFO) in a received data packet. From the CFO estimate, an SFO estimate is derived, wherein the SFO is approximately equal to fs multiplied by said CFO estimate, and divided by fc. An SFO phase correction is generated according to the SFO estimate for each kth tone in a data stream. The SFO phase correction is then applied to each received data stream.

Abstract: Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.

Abstract: The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CT??ADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CT??ADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CT??ADC loop. In one embodiment of the invention, random noise is added to the quantizer input.

Abstract: Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in accordance with the present invention apply a variety of techniques that may include, in various applications, collapsing two multi-round authentication algorithm (e.g., SHA1 or MD5 or variants) processing rounds into one; reducing operational overhead by scheduling the additions required by a multi-round authentication algorithm in such a matter as to reduce the overall critical timing path (“hiding the ads”); and, for a multi-loop (e.g., HMAC) variant of a multi-round authentication algorithm, pipelining the inner and outer loops.

Abstract: A multimode wireless communication includes a digital baseband processing module, an analog to digital converter module, a digital to analog converter module, a first radio section, and a second radio section. The digital baseband processing module is operably coupled to convert outbound data into outbound digital baseband signals and to convert inbound digital baseband signals into inbound data. The analog to digital converter module is operably coupled to convert inbound analog baseband signals into the inbound digital baseband signals. The digital to analog converter module is operably coupled to convert the outbound digital baseband signals into outbound analog baseband signals. The first radio section is operably coupled to convert the outbound analog baseband signals into first outbound radio frequency (RF) signals and to convert first inbound RF signals into the inbound analog baseband signals when the wireless communication device is in a first mode of operation.

Abstract: A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of transmit status or excessive interrupt servicing. The queue monitoring implements an interrupt mechanism that generates an interrupt if one or more of the transmit queues has gone from a non-empty state to an empty state, and remained in the empty state for a (programmable) period of time. The combination of queue status checking (when adding new transmit data) with the queue monitoring interrupt mechanism removes the need for periodic polling of queue status and handling of interrupts generation on the completed transmission of data from one or more transmit buffer.

Abstract: A system and method for personal video recording (PVR) is provided for recording digitally encoded streams, and for playing back and decoding the recorded streams. The PVR system may receive the digitally encoded streams from a digital cable box or a network server. The system enables trick modes including fast forward and reverse mode displays at various speeds. The system an method for PVR may also be applied to digitally encoded streams without I-pictures, such as, for example, progressive refresh streams or HITS streams. Reverse decode and display may be implemented by starting at a suitable entry point, decoding quickly up to the point of the desired picture, and displaying the result, and repeating the process. Index tables of entry points may be used for proper operation in some modes where the entry points are entry pictures (E-pictures) which start a pattern of progressively refreshing I-slices.

Abstract: A system and method for reducing power consumption in digital circuitry by reducing the amount of unnecessary switching in such circuitry. An aspect of the present invention provides a switching-reduction circuit that outputs a signal to a subsequent digital circuit. The value of the signal may depend on the relevance of the signal value to a next output of the subsequent digital circuit. A method according to various aspects of the present invention includes receiving a next input signal. The method further includes determining whether the next input signal may be relevant to a next output of a subsequent digital circuit. The method further includes providing the next input signal to the subsequent digital circuit when the next input signal may be relevant to the next output of the subsequent digital circuit, and providing a previous signal to the subsequent digital circuit when the next input signal will not be relevant to the next output of the subsequent digital circuit.

Abstract: Method of processing a transmitted encoded media data stream is received. If a data element arrives prior to, or at, a predetermined playout deadline, the data element is decoded, the media represented by the decoded data element is played, and the data element is provided to a decoder state machine to update a decoder state. If a data element arrives after the predetermined playout deadline, the data element is provided to the decoder state machine to update the decoder state. In one embodiment, if the specified data element fails to arrive by the playout deadline, a subsequently received data element is saved in memory. Then, if the specified data element arrives after the predetermined playout deadline, the specified data element and the saved, subsequently received, data element are provided to the decoder state machine to update the decoder state.

Abstract: A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data.

Abstract: A method for conditionally performing a SIMD operation causing a predetermined number of result objects to be held in a combination of different ones of a plurality of destination stores, the method comprising receiving and decoding instruction fields to determine at least one source store, a plurality of destination stores and at least one control store, said source and destination stores being capable of holding one or a plurality of objects, each object defining a SIMD lane. Conditional execution of the operation on a per SIMD lane basis is controlled using a plurality of pre-set indicators of the at least one control store designated in the instruction, wherein each said pre-set indicator i controls a predetermined number of result lanes p, where p takes a value greater than or equal to two. A predetermined number of result objects are sent to the destination stores such that the predetermined number of result objects are held by a combination of different ones of the plurality of destination stores.

Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.

Abstract: A system and method is presented that uses hardware at a central node to determine if bandwidth being provided to a remote node in accordance with an unsolicited grant service (UGS) flow requires adjustment. In one embodiment, the hardware performs this function by comparing information in two consecutively-received UGS extended headers from the same remote device. If the information in the current and previous UGS extended headers differ, then an indication is provided to software of the central node that the bandwidth being provided to the remote node requires adjustment.