Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.

Abstract: A system and method is presented that uses hardware at a central node to determine if bandwidth being provided to a remote node in accordance with an unsolicited grant service (UGS) flow requires adjustment. In one embodiment, the hardware performs this function by comparing information in two consecutively-received UGS extended headers from the same remote device. If the information in the current and previous UGS extended headers differ, then an indication is provided to software of the central node that the bandwidth being provided to the remote node requires adjustment.

Abstract: A method and system for combining requests for data bandwidth by a data source for transmission of data over a wireless communication medium is provided. A central node receives one or more bandwidths requests from one or more data sources via wireless communication. A scheduler then combines one or more bandwidths requests from the same data source to create a single data burst bandwidth. The central node then grants the data burst bandwidth to the appropriate data source via wireless communication.

Abstract: A method for forming and packaging an integrated circuit having a plurality of circuit components on a semi conductive substrate die. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an Electro Static Discharge (ESD) protection inductor, and a chip pad. The chip pad couples to the tuning node. The ESD protection inductor communicatively couples between the tuning node and a rail formed on the semi conductive substrate die. The ESD protection inductor provides ESD protection prior to packaging of the semi conductive substrate die or in some cases prior to the installation of the packaged die on a PC board or the equivalent. The bond wire couples between the chip pad and a package pad and serves as a tuning inductor for the circuit.

Abstract: A communication system includes a supervisory node (e.g., a headend) and one or more remote nodes (e.g., cable modems). The supervisory node or a remote node monitors a characteristic associated with the communication system. Remote node transmits an upstream communication among a plurality of physical upstream channels based on the characteristic. The average transmit power used to transmit the upstream communication among the plurality of physical upstream channels is no greater than the average transmit power that would be necessary to transmit the upstream communication using a single physical upstream channel at a lower data rate.

Abstract: A power amplifier power amplifier includes a transconductance stage and a cascode stage. The transconductance stage that is operable to receive an input voltage signal and to produce an output current signal. The transconductance stage includes a first Metal Oxide Silicon (MOS) transistor having a first gate oxide thickness and a first channel length. The cascode stage communicatively couples to the transconductance stage and is operable to receive the output current signal and to produce an output voltage signal based thereupon. The cascode stage includes a second MOS transistor having a second gate oxide thickness and a second channel length.

Abstract: A circuit is formed to steer current in and out of an inductive load in a manner that enables an amplifier to provide a plurality of gain steps without modifying an LC time constant for the circuit and, therefore, without modifying the tuning or frequency of oscillation for the circuit. A first group of MOSFETs are coupled in parallel and define the circuit current flow. A second group of MOSFETs are coupled in parallel to each other and in series to an impedance device. A third group of MOSFETs coupled to steer current in and out of the impedance device to affect the output signal coupled to one end of the impedance device. The transistors in the second and third groups of MOSFETs are selectively activated to control the amount of current that goes through the impedance device.

Abstract: A radio transceiver includes circuitry that enables received RF signals to be down-converted to baseband frequencies and baseband signals to be up-converted to RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a temperature sensing module that produce accurate voltage level readings may be mapped into corresponding temperature values. A processor, among other actions, adjusts gain level settings based upon detected temperature values. One aspect of the present invention further includes repetitively inverting voltage signals across a pair of semiconductor devices beings used as temperature sensors to remove a common mode signal to produce an actual temperature-voltage curve. In one embodiment of the invention, the circuitry further includes a pair of amplifiers to facilitate setting a slope of the voltage-temperature curve.

Abstract: A system and method demodulate N QAM signals (N being a positive integer equal to or greater than 1) substantially simultaneously using, for example, one or two oscillators, regardless of how many QAM signals need to be demodulated.

Abstract: Efficient construction of LDPC (Low Density Parity Check) codes with corresponding parity check matrix having CSI (Cyclic Shifted Identity) sub-matrices. These constructed LDPC codes can be implemented in multiple-input-multiple-output (MIMO) communication systems. One LDPC code construction approach uses CSI sub-matrix shift values whose shift values are checked instead of non-zero element positions within the parity check matrix (or its corresponding sub-matrices). When designing an LDPC code, this approach is efficient to find and avoid cycles (or loops) in the LDPC code's corresponding bipartite graph. Another approach involves GRS (Generalized Reed-Solomon) code based LDPC code construction. These LDPC codes can be implemented in a wide variety of communication devices, including those implemented in wireless communication systems that comply with the recommendation practices and standards being developed by the IEEE 802.11n Task Group (i.e., the Task Group that is working to develop a standard for 802.

Abstract: Calibration of a phase locked loop and applications thereof within a radio frequency integrated circuit begins by determining an intersection of an up current and down current produced by a charge pump within the phase locked loop. The RFIC then determines a reference voltage corresponding to the intersection, which varies from an ideal voltage of VDD/2 based on process variations. The RFIC then offsets a control voltage to the voltage control oscillator (VCO) of the phase locked loop based on the reference voltage. Accordingly, by determining the offset of the actual intersection from the ideal intersection, the control voltage to the VCO may be adjusted thereby calibrating the phase locked loop for more linear performance.

Abstract: A testing system performs simultaneous automated at-speed testing of a plurality of devices that generate serial data signals having gigabit per second baud rates coupled to a DIB and device connectors on the DIB. The testing system includes a rider board including rider board connectors coupled to corresponding ones of the device connectors, an individual set of multiplexers coupled to each one of said rider board connectors, a controller coupled to each of said set of multiplexers, and an internal testing system including a tester and testing system multiplexers, said tester being coupled to each of said set of multiplexers via said testing system multiplexers.

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract: A Radio Frequency (RF) circuit includes an active portion and a tuned portion. The active portion receives an RF signal and that operates upon the RF signal. The tuned portion couples to the active portion and includes a first inductor, a second inductor, and a switch. When the switch is closed, the second inductor couples to the first inductor and the tuned portion has first tuning characteristics. When the switch is open, the second inductor is decoupled from the first inductor and the tuned portion has second tuning characteristics. The tuned portion may include lumped or parasitic capacitance. The tuned portion alternately includes an inductor having a first terminal, a second terminal, an intermediate tap, and a switch that couples between the second terminal and the intermediate tap. When the switch is closed the tuned portion has first tuning characteristics and when the switch is open, the tuned portion has second tuning characteristics.

Abstract: A system and technique for detecting a device that requires power is implemented with a power detection station. The power detection system includes a detector having an output and a return which are coupled together by the device when the device requires power. The detector includes a word generator for generating test pulses for transmission to the device via the detector output, and a comparator for comparing the detector output with the detector return. The power detection station has a wide variety of applications, including by way of example, a switch or hub.

Abstract: Methods and apparatus for switching between a live video decoding and a recorded playback in a digital video and recording system. A received video data stream is transmitted to a first-in first-out video decoder buffer without first looping the video data stream through a playback buffer. The video data stream is transmitted from the video decoder buffer to a video decoder. If a “pause” command is received, the video data stream is transmitted to a first-in first-out playback buffer, while continuing to transmit the video data stream to the video decoder buffer. Transmission of the video data stream to the video decoder buffer is halted when the video decoder buffer fills up. The last byte of the video data stream that was transmitted to the video decoder buffer is marked. If a “play” command is received, the video data stored in the video decoder buffer is transmitted to the video decoder.

Abstract: A system, method, and apparatus for dividing and truncating a dividend by a divisor, wherein the magnitude of the divisor is a positive power of two, e.g., 2x, is presented herein. If the divisor is positive, the sign bit of the dividend is concatenated x times and added to the dividend. If the divisor is negative, the dividend is inverted, the sign bit of the inverted dividend is concatenated x times, and added to the inverted dividend. The sign bit of the divisor is also added to the sum and the result is right shifted x times. If the signs of the divisor and the dividend are the same, a zero is shifted into the most significant bit during each right shift. If the signs of the divisor and the dividend are different, the most-significant-bit (sign bit) of the result of addition is shifted into the most significant bit during each right shift.

Abstract: A method and system for processing packets allows consolidation of security processing. Security processing is performed in accordance with multiple security policies. This processing is done in a single front end processing block. Different security processes can be performed in parallel. Processing overhead is reduced by eliminating the need to redundantly check packet characteristics to assess the different security requirements imposed by security policies. Further, the present invention also substantially reduces the CPU cycles required to transport data back and forth from memory to a cryptographic coprocessor.

Abstract: A method of manufacturing an on-chip transformer balun includes creating, on a semiconductor substrate, a primary winding having at least one substantially symmetrical primary turn on a first dielectric layer and at least one metal bridge on a second layer. A secondary winding is created on the semiconductor substrate, the secondary winding having at least one substantially symmetrical secondary turn on a third dielectric layer and at least one metal bridge on a fourth dielectric layer. In an alternative embodiment, the primary winding has at least one first primary turn on a first dielectric layer and at least one second primary turn on a second dielectric layer and at least one via that operably connects the first primary turn to the second primary turn. The secondary winding has at least one first secondary turn on a third dielectric layer and at least one second secondary turn on a fourth dielectric layer.

Abstract: A method and system for reducing noise in a video stream comprising images divided into macroblocks, where each macroblock includes luma and chroma blocks and each block is comprised of pixels. The method comprises determining correlation of a macroblock with a reference macroblock, comparing its motion vectors to a predetermined threshold, computing a residual signal of the macroblock by subtracting the macroblock from a predicted macroblock, computing a variance of a residual signal of the macroblock, comparing the variance of the residual signal to another predetermined threshold, determining a filter strength for the macroblock based on one or more of factors such as correlation, motion vector size and variance of the residual signal and filtering the macroblock using a filter of appropriate strength.