Abstract: A method and system for reducing noise in a video stream comprising images divided into macroblocks, where each macroblock includes luma and chroma blocks and each block is comprised of pixels. The method comprises determining correlation of a macroblock with a reference macroblock, comparing its motion vectors to a predetermined threshold, computing a residual signal of the macroblock by subtracting the macroblock from a predicted macroblock, computing a variance of a residual signal of the macroblock, comparing the variance of the residual signal to another predetermined threshold, determining a filter strength for the macroblock based on one or more of factors such as correlation, motion vector size and variance of the residual signal and filtering the macroblock using a filter of appropriate strength.

Abstract: Discriminating a modulation type based upon a predetermined portion of symbols for a received encoded signal. While receiving the encoded signal, at least a first and a second cumulative soft metrics are generated using the plurality of symbols over a predetermined portion of the received encoded signal. The first cumulative soft metric is compared with the second cumulative soft metric to generate or provide a discriminated modulation type. With the discriminated modulation type, the signal field is decoded, allowing for decoding of the accompanying data payload with the encoded signal.

Abstract: Methods and systems for estimating available bandwidth on an internet access network are presented. A method includes: (a) transmitting one or more Internet Control Message Protocol (ICMP) echo request packets to a device residing on the network at a first bit rate; (b) receiving one or more ICMP echo reply packets corresponding to the one or more ICMP echo request packets responsive to step (a); and (c) determining a second bit rate for the one or more ICMP echo reply packets. If the second bit rate is less than the first bit rate, available bandwidth is estimated based on the second bit rate. If the second bit rate is not less than the first bit rate, steps (a), (b) and (c) are repeated. The first bit rate is increased for each iteration, until the second bit rate is less than the first bit rate, and then available bandwidth is estimated based on the second bit rate.

Abstract: An apparatus provides a local oscillator signal based on a selected channel of an RF input signal. For example, the apparatus can set a frequency of the local oscillator signal based on the selected channel. Digital circuitry can be used to generate the local oscillator signal. For instance, the digital circuitry can provide a digital representation of the local oscillator signal. A DAC can convert the digital representation to an analog signal. Other circuitry can provide first and second quadrature components of the local oscillator signal, based on the analog signal.

Abstract: A method, system and computer program product for a generic data storage interface for local and remote networked storage is provided. It comprises providing a data storage interface accessible by an operating system, transmitting data from an application running on the operating system to the data storage interface and selectively storing the data using the same data storage interface in either a local or a remote networked storage location. Firmware for the common data storage interface assigns a unique identifier that classifies an I/O request as a local or remote networked I/O request and adds the I/O request to a common stack for local and remote networked data storage elements. When an I/O request is removed from the stack, the unique identifier is used to identify the I/O request as a local or remote networked I/O request. Local I/O requests are executed via a local bus such as PCI, or SCSI.

Abstract: A method and apparatus for communicating between devices is described. In one embodiment, the method comprises running two or more instances of a switch MAC sublayer on a switch and managing the two or more instances of the switch MAC sublayer as multiple logical access points inside the switch.

Abstract: A receiver front end includes a plurality of in-phase and quadrature phase receive processing blocks operable at first and second frequency bands and further includes a plurality of filtering and amplification blocks disposed within a corresponding ingoing signal path, a plurality of received signal strength indicator (RSSI) blocks coupled to receive an ingoing analog signal from a corresponding plurality of nodes disposed throughout the ingoing signal path, each of the plurality of RSSI blocks producing a signal strength indication, and wherein a baseband processor is operable to receive a selected signal strength indication and to produce at least one gain setting to at least one amplification block within the in-phase or quadrature phase receive processing blocks. In operation, the baseband processor receives a signal strength indication from each RSSI block to determine a total amount of gain and appropriate gain distribution within the receive signal path.

Abstract: A timing recovery circuit comprises a data-driven phase detector and a digital loop filter. The data-driven phase detector is operably coupled to determine at least a phase difference between an input signal and a feedback clock signal to produce a difference signal. Determining the phase difference can comprise digitally determining a timing difference between the input signal and the feedback clock signal, digitally determining a transition of the input signal to produce a transition detect signal, and digitally updating the timing difference based on the transition detect signal and the feedback clock signal. The timing difference can be digitally updated by pre-filtering the timing difference BY TAKING EVERY N TRANSITON OR AVERAGE OF EVERY N TRANSITIONS at a digital pre-filter, based on a pre-filter clock signal produced from the transition detect signal and the feedback clock signal, to produce the difference signal.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: An integrated circuit ground system includes an integrated circuit (IC) ground connection, first and second IC package pins, first and second printed circuit board (PCB) pads, a PCB ground connection, and a resonant circuit. The IC ground connection is fabricated on a substrate of an integrated circuit. The first IC package pin is operably coupled to the IC ground connection via a first bond wire. The second IC package pin is operably coupled to the IC ground connection via a second bond wire. The second PCB pad is operably coupled to the second IC package pin to provide a low impedance DC ground connection for the integrated circuit to the printed circuit board. The resonant circuit is operably coupling the first IC package pin to the first PCB pad, wherein the resonant circuit is tuned to resonant with the first bond wire at high frequency range to provide a low impedance AC ground connection for the integrated circuit to the printed circuit board within the high frequency range.

Abstract: A shared memory system includes a plurality of processing nodes and a packetized input/output link. Each of the plurality of processing nodes includes a processing resource and memory. The packetized I/O link operably couples the plurality of processing nodes together. One of the plurality of processing nodes is operably coupled to: initiate coherent memory transactions such that another one of plurality of processing nodes has access to a home memory section of the memory of the one of the plurality of processing nodes; and facilitate transmission of a coherency transaction packet between the memory of the one of the plurality of processing nodes and the another one of the plurality of processing nodes over the packetized I/O link.

Abstract: AN RF diversity antenna coupling structure includes a differential low noise amplifier, a differential power amplifier, a first switch coupled to a first antenna, a second switch coupled to a second antenna, a first transformer, a second transformer, a transformer balun. The first transformer includes a primary winding and a secondary winding, wherein the primary winding of the first transformer is operably coupled to a differential output of the power amplifier, and wherein the secondary winding of the first transformer has a desired output impedance. The second transformer includes a primary winding and a secondary winding, wherein the primary winding of the second transformer is operably coupled to a differential input of the low noise amplifier, and wherein the secondary winding of the second transformer has a desired output impedance.

Abstract: Codec structures for achieving two-stage prediction and two-stage noise spectral shaping at the same time, resulting in a Two-Stage Noise Feedback Coding (TSNFC) method. One approach combines two predictors into a single composite predictor; and derives appropriate filters for use in a conventional single-stage NFC codec structure. Another approach duplicates a conventional single-stage NFC codec structure in a nested manner, thereby decoupling the operations of the long-term prediction and long-term noise spectral shaping from the operations of the short-term prediction and short-term noise spectral shaping.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

Abstract: A low noise divider module includes a divider chain and a retiming module. The divider chain includes a plurality of cascaded dividers and a plurality of load logic gates. The plurality of cascaded dividers are operably coupled to divide an input oscillation by a divider value, which is programmable, to produce a divided output oscillation based on the load signals provided by the logic gates. The retiming module includes a duty cycle module and a jitter reduction module. The duty cycle module is coupled to produce a duty cycle controlled output oscillation based on a representation of the divided output oscillation produced by the divider chain in accordance with a duty cycle setting signal. The jitter reduction module is operably coupled to produce a low jitter output oscillation from the duty cycle controlled output oscillation based on the input oscillation and the duty cycle setting signal.

Abstract: A via provides a plurality of electrical connections between conductors on different layers of a circuit board. The via includes an opening through the circuit board formed by a plurality of substantially partially overlapping bores. An electrically conductive plating is formed on an inner surface of the opening. The plating forms a plurality of distinct electrically conductive paths.

Abstract: A method for adjusting a received signal strength indication (RSSI) begins by obtaining a first RSSI value of a first signal, wherein the first signal has a known first power level. The method continues when the first RSSI value does not substantially correspond to the known first power level by adjusting an RSSI intercept value of an RSSI curve until the first RSSI value substantially corresponds to the known first power level. The method continues by obtaining a second RSSI value of a second signal, wherein the second signal has a known second power level. The method continues when second RSSI value does not substantially correspond to the known second power level by adjusting slope of the RSSI curve until the second RSSI value substantially corresponds to the known second power level.

Abstract: Systems and methods that provide remote access are described. In one embodiment, a system may include, for example, a plurality of communication devices and a media device. The plurality of communication devices may be operatively coupled to a network and may include, for example, a native communication device. The media device may be operatively coupled to the native communication device and the network. The media device may be associated with the native communication device and the network and may be capable of exchanging media content with the plurality of communication devices and the network. A profile of the media device may be stored in at least one of the media device and the native communication device. The profile may include, for example, information related to managing the media content when the media device is roaming.

Abstract: A linear fractional-N synthesizer includes phase and frequency detection module, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a fractional-N divider. The phase and frequency detection module is operably coupled to produce a charge up signal, a charge down signal, or an off signal based on a phase difference and/or a frequency difference between a reference oscillation and a feedback oscillation. The charge pump circuit is operably coupled to produce a positive current when the charge up signal is received, a negative current when the charge down signal is received, and a non-zero offset current when the off signal is received. The charge pump includes a resistor and a control module. The resistor provides the non-zero offset current and the control module maintains the non-zero offset current at a substantially constant value.

Abstract: A computer apparatus for receiving a removable communication card such as a radio card or a modem card. A radio or modem is self-contained inside a housing of the communication card and has an electrical interface for communicating information to and from the computer apparatus. The computer apparatus receives the communication card such that it engages the electrical interface. These contacts automatically connect the communication card to an appropriate antenna, telephone or telephone line. A radio communication card is connected to the appropriate antenna for the type and frequency of the radio. A modem card is connected to a standard telephone line, a cellular phone, or an antenna for a cellular phone if the cellular phone is also disposed within the housing of the modem communication card. Additionally, a switching matrix can be used to connect one set of contacts on a radio card or a modem card to one or more of a plurality of antennas and telephone lines.