Abstract: A system, method, and apparatus for efficient rounding of signed numbers is presented herein. If the divisor is positive, the dividend is added to one half of the magnitude of the divisor. If the divisor is negative, the complement of the dividend is added to one half of the magnitude of the divisor. If the dividend is negative, and the divisor is also negative, one is added to the sum of the inverted dividend and one-half of the magnitude of the divisor. If the dividend is negative and the divisor is positive, one is subtracted from the sum of the dividend and one-half the magnitude of the divisor. The result is then right shifted x times. If the signs of the divisor and dividend are different, a most-significant-bit(sign-bit) of the result is shifted in as the most significant bit during each right shift. Otherwise, a “0” is shifted in.

Abstract: A power amplifier includes a transconductance stage and a modulation detection and bias determination module, and may include a cascode stage. The modulation detection and bias determination module operably couples to the transconductance stage and to the cascode stage when present and is operable to detect modulation characteristics of an signal operated upon by the transconductance stage. The modulation detection and bias determination module is also operable to controllably bias the transconductance stage and/or the cascode stage when present based upon detected modulation characteristics. The detected modulation characteristics are typically determined based upon a measured signal level, e.g., voltage level, current level, or power level, of the signal operated upon by the transconductance device. For non-constant envelope modulations, the signal level varies over time with the modulation envelope. The operational characteristics of the power amplifier, e.g.

Abstract: A system and method are used to determine connectivity and/or cable faults of a cable. A signal transmitting and receiving system is coupled to the cable. An analog-to-digital converter (ADC) coupled to the signal transmitting and receiving system. A TDR system coupled to the ADC and a memory, and a controlling system coupled to at least one of the ADC, the TDR system, and the signal receiving and transmitting system.

Abstract: Aspects of the invention provide a system and method for communicating in a hybrid wired/wireless local area network. A method for communicating in a hybrid wired/wireless local area network may include sending a first messaging protocol message between a first switch and a first access point, and/or the first switch and a second switch. In response to the first messaging protocol message, receiving at least a second messaging protocol message from the first access point, the first switch, and/or the second switch. The first, second, and a third messaging protocol message may be used to control the first switch, the second switch, a first access point, a second access point, and one or more access devices.

Abstract: A host-side wireless interface services communications between a wireless user input device and a serviced host. The host-side wireless interface includes a wireless network interface, a host interface, and may include additional components. The wireless network interface wirelessly communicates with the wireless user input device. The host interface communicatively couples to the wireless interface and to the serviced host. When the serviced host initiates bootstrap operations via a Basic Input/Output System (BIOS), the host interface operates in a BIOS host interface mode to allow input from the wireless user input device to the BIOS during the bootstrap operations. Further, when the serviced host initiates Operating System (OS) operations, the host interface operates in an OS host interface mode, wherein the OS host interface mode differs from the BIOS host interface mode.

Abstract: A system and method for provide a stable gain from an adaptive gain control device in a signal path. An echo canceller is also located in the signal path, and is used to provide performance information regarding losses in the signal. This performance information is fed to the automatic gain control device via a connection. The automatic gain control device thereafter uses the performance information to determine a maximum gain that might be provided based upon losses cause by echo conditions. The gain however is limited in order to provide for a stable system. The performance information includes a loss rate that includes a combination of the echo return loss and the echo return loss enhancement.

Abstract: Embodiments of the invention may provide a method for implementing an adaptive multimode media queue. A mode of operation may be determined for a received media stream based on a sampling rate of the media stream. The mode of operation may be a wideband mode and/or a narrowband mode. Depending on the determined mode, the adaptive multimode media queue may be partitioned into a low band media queue and a high band media queue. A wideband media stream split into a high band and a low band is buffered into the adaptive multimode media queue wherein the high band is stored in the high band media queue, and the low band is stored in the low band media queue. The high band media queue and low band media queue may be a contiguous memory block within the adaptive multimode media queue. The received media stream, which may have different sampled data rates may be buffered within the partitioned adaptive multimode media queue.

Abstract: A two way communication system is adapted for compatible inter-operation of a plurality of devices operating in accordance with a plurality of protocols. The communication system includes a first group of one or more remote devices that interface with a local host in accordance with a first protocol and a second group of one or more remote devices that interface wit the local host in accordance with a second protocol. The local host includes a protocol processor that identifies transmissions from the first and second groups of remote devices and routes transmissions from the first group of remote devices to a first processor operating in accordance with the first protocol and also routes transmissions from the second group of remote devices to a second processor operating in accordance with the second protocol.

Abstract: A system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the majority of the collected data to external system memory, which is typically comprised of commodity memory chips. Since this external system memory is already in use by other system functions, utilizing such unused regions of this external memory increases overall hardware efficiency, while achieving lower ASIC manufacturing cost.

Abstract: Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface coupled to the surface of the substrate. An area of the surface of the stiffener can be greater than, equal to, or less than an area of the surface of the substrate. A thermal connector is coupled to the surface of the stiffener through the opening. A surface of the thermal connector is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. The thermal connector can have a height such that the thermal connector extends into a cavity formed in a surface of the PCB when the BGA package is mounted to the PCB. Alternatively, the stiffener and thermal connector may be combined into a single piece stiffener, wherein the stiffener has a protruding portion.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: A timing recovery system and method for accelerated clock synchronization of remotely distributed electronic devices is provided. The system includes a phase locked loop, a linear estimator and control logic. The method includes sampling a clock signal received from an electronic device, applying a linear estimation technique to estimate the frequency and phase of the received signal and providing those estimates to a phase locked loop to accelerate the phase locked loop acquisition rate and secure signal lock quickly.

Abstract: Methods and apparatus are provided for efficiently normalizing and denormalizing data for cryptography processing. The normalization and denormalization techniques can be applied in the context of a cryptography accelerator coupled with a processor. Hardware normalization techniques are applied to data prior to cryptography processing. Context circuitry tracks the shift amount used for normalization. After cryptography processing, the processed data is denormalized using the shift amount tracked by the context circuitry.

Abstract: A Radio Frequency (RF) receiver includes a low noise amplifier (LNA) and a mixer coupled to the output of the LNA. The gain of the LNA is adjusted to maximize signal-to-noise ratio of the mixer and to force the mixer to operate well within its linear region when an intermodulation interference component is present. The RF receiver includes a first received signal strength indicator (RSSI_A) coupled to the output of the mixer that measures the strength of the wideband signal at that point. A second received signal strength indicator (RSSI_B) couples after the BPF and measures the strength of the narrowband signal. The LNA gain is set based upon these signal strengths. By altering the gain of the LNA by one step and measuring the difference between a prior RSSI_B reading and a subsequent RSSI_B? reading will indicate whether intermodulation interference is present.

Abstract: Communication decoder employing single trellis to support multiple code rates and/or multiple modulations. A single trellis is employed by the decoder to decode a plurality of encoded symbols. Each of the plurality of encoded symbols is governed by a rate control. A rate control sequence, having a period, is used to decode the plurality of encoded symbols that may be arranged within a frame. Various parameters of the plurality of encoded symbols may vary on a symbol by symbol basis; these parameters may include modulation, constellation, mapping, and/or bandwidth efficiency. For example, various symbols may be encoded differently, yet they may all be decoded using the same trellis. The functionality of this decoder may be implemented within a variety of different decoder embodiments including a trellis code modulation (TCM) decoder, a turbo trellis code modulation (TTCM) decoder, and/or a parallel concatenated turbo code modulation (PC-TCM) decoder.

Abstract: Cancellation of interference in a communication system with application to S-CDMA. A relatively straight-forward implemented and computationally efficient approach of selecting a predetermined number of unused codes is used to perform weighted linear combination selectively with each of the input spread signals in a multiple access communication system. If desired, the predetermined number of unused codes is always the same in each implementation. Alternatively, the predetermined number of unused codes is selected from within a reordered code matrix using knowledge that is shared between the two ends of a communication system, such as between the CMs and a CMTS. While the context of an S-CDMA communication system having CMs and a CMTS is used, the solution is generally applicable to any communication system that seeks to cancel narrowband interference. Several embodiments are also described that show the generic applicability of the solution across a wide variety of systems.

Abstract: A voltage regulator circuit includes a single high voltage regulator, and a plurality of parallel low voltage regulators capable of receiving an intermediate voltage from the high-voltage regulator, and capable of outputting a regulated output voltage. The intermediate voltage is no higher than a breakdown voltage of the low voltage regulators.

Abstract: A signal processing system which discriminates between voice signals and data signals modulated by a voiceband carrier. The signal processing system includes a voice exchange, a data exchange and a call discriminator. The voice exchange is capable of exchanging voice signals between a switched circuit network and a packet based network. The signal processing system also includes a data exchange capable of exchanging data signals modulated by a voiceband carrier on the switched circuit network with unmodulated data signal packets on the packet based network. The data exchange is performed by demodulating data signals from the switched circuit network for transmission on the packet based network, and modulating data signal packets from the packet based network for transmission on the switched circuit network. The call discriminator is used to selectively enable the voice exchange and data exchange.

Abstract: The present invention relates to a system and method for generating a first clock frequency for a plurality of digital data bursts compressed in time, where each of the plurality of digital data bursts has been multiplexed into one of a plurality of data blocks of higher speed digital data. The system and method includes acquiring the width in data elements of a digital data burst and the width in data elements of a data block of higher speed digital data. The width of one period of a clock pulse is computed at the first clock frequency. A clock pulse is generated at the first clock frequency.

Abstract: An environmental-compensated oscillator includes a reference clock waveform generator; a phase locked loop receiving the reference clock waveform and outputting a phase locked clock waveform; and a sensor outputting a voltage corresponding to an environmental parameter of the generator. The voltage is used by the PLL to compensate the phase locked clock waveform. The PLL includes a phase detector, a charge pump coupled to an output of the phase detector, a low pass filter coupled to an output of the charge pump, a voltage controlled oscillator (“VCO”) coupled to an output of the low pass filter, and a feedback path coupled between an output of the VCO and the phase detector, wherein the feedback path includes a phase rotator capable of fine tuning an output frequency of the VCO responsive to a frequency of an input clock. An accumulator is coupled to the phase rotator and supplies the input clock to the phase rotator. The phase rotator finely tunes the VCO output frequency.