Abstract: Angle estimation for modulated signal. A novel compensation technique is presented by which angle estimation may be performed for a modulated signal. More specifically, the angle between a constellation corresponding to a received signal and a constellation corresponding to a received signal may be very efficiently estimated using any one of the possible embodiments corresponding to various aspects of the invention. After this angle has been estimated, the received signal or the expected constellation may be rotated (or de-rotated) to compensate for this angular difference. In doing so, better estimates of the information bits that are demodulated and decoded from the received signal may be made.

Abstract: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform band-select tuning of the VCO. The gain compensator compensates for the variable VCO gain by generating a charge pump reference current that is based on the same capacitor control signal that controls the fixed capacitors in the LC circuit. The gain compensator generates the charge pump reference current by replicating a reference scale current using unit current sources. The number of times the reference scale current is replicated is based on the fixed capacitance that is switched-in to the LC circuit and therefore the frequency band of the PLL.

Abstract: Energy detect with auto pair select for energy management without ‘a priori’ knowledge of the wire pairs connectivity. The energy detect with auto pair select is operable within systems performing automatic detection of connectivity in systems that employ the Ethernet based media dependent interface crossover (MDIX). Where there has been some cross-over of pairs within the system, a situation not uncommon in many networks, the energy detect with auto pair select is operable to perform energy management without knowledge of the pair connectivity. Selection or detection of coupled wire pairs is acquired by energy detection of coupled wire pairs via a state machine that analyzes a qualified energy level.

Abstract: Multiple-input-multiple-output (MIMO) timing recovery. A novel approach is presented to perform timing recovery when processing the multiple received signals within a MIMO communication device. This may be implemented for a singular received signal, or a plurality of received signal streams. In addition, this timing recovery may be performed in conjunction with carrier detection to provide more robust performance. Alternatively, indicia and/or signals corresponding to carrier detection of these signals may be provided to timing recovery functionality from carrier detection functionality external to the timing recovery functionality. Certain processing and analysis is performed on a modified correlation function that is generated using samples of moving windows that pass over symbols of a packet.

Abstract: Carrier detection applicable for SISO, MIMO, MISO, and SIMO communications. A novel approach is presented to perform carrier detection for a signal found in any of a wide variety of communication systems including single-input-multiple-output (SISO), multiple-input-multiple-output (MIMO), multiple-input-single-output (MISO) single-input-multiple-output (SIMO), communication systems. This novel approach to performing carrier detection is more robust than those approaches existent in the art. By employing normalization with respect to power in determined a modified correlation function, there is less susceptibility to false detects. Also, this approach is quite robust to any circuitry DC offsets that may undesirably exist within a communication device that undergoes operational changes due to a variety of factors including environmental perturbations and/or changes in processing circuitry within the communication device (e.g., changes in gain control).

Abstract: The method and apparatus in accordance with the present invention receives bits, writes the bits row-by-row in a matrix, reads the bits column-by-column from the matrix, groups and rotates the bits read column-by-column from the matrix so as to evenly separate the bits in position, frequency, space over one symbol period.

Abstract: A microprocessor, including a plurality of registers and an instruction execution module which is adapted to process a sequence of conditional tests. The module uses an instruction set that has the following instructions: A test-and-condition instruction which evaluates each of the conditional tests as true or false and responsive thereto sets respective values in the registers. A priority-test-branch instruction, which causes the instruction execution module, responsive to one of the conditional tests evaluating as true and to the respective values in the registers, to execute a priority code module. A combination-test-branch instruction, which causes the instruction execution module, responsive to evaluations of the conditional tests and to the respective values in the registers, to execute a combination code module.

Abstract: A high frequency peak detector includes an operational amplifier, a transistor, a capacitor, and an average to peak conversion module. A first inverting input of the operational amplifier receives a high frequency input signal, a second inverting input of the operational amplifier receives a common mode voltage of the high frequency signal, and a non-inverting input of the operational amplifier is coupled to the output of the operational amplifier. A gate of the transistor is operably coupled to the output of the operational amplifier and the source of the transistor is operably coupled to a power supply. The capacitor is operably coupled to the drain of the transistor to provide an analog signal representing an average peak to common mode value of the high frequency signal and to a circuit ground. The average to peak conversion module determines a peak value of the high frequency signal based on the analog signal and the common mode value.

Abstract: Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another embodiment a FIFO is presented that can be set and/or reset asynchronously. Other embodiments are disclosed wherein the read and write pointers are effectively monitored to ensure proper timing relationship, to detect loss of clock as well as to detect other abnormal FIFO conditions.

Abstract: A method for identifying a bad GSM speed frame and simultaneously maintaining a frame erasure rate below a specified value. The method is based upon a joint use of four signal quality metrics: (1) frame CRC parity check; (2) estimated burst signal-to-noise ratio; (3) estimated frame bit error count; and (4) stealing flag values of a frame. Another feature includes providing an improved estimated burst signal-to-noise ratio.

Abstract: A method for selectively deskewing data traveling through a bus in a network device is disclosed. Bit-level data is received from each data line of a plurality of data lines of the bus. Vertical line information is detected for the plurality of data lines to determine if there is a match with a training pattern. A skew distance is calculated once there is a match with the training pattern. Then, the plurality of data lines are bit aligned based on the skew distance.

Abstract: Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit. The vector unit can comprises a plurality of value processing units and a scalar result unit. The scalar unit can comprise a scalar register file. Communication between the vector unit and the scalar unit is enabled by allowing the vector unit to access the scalar register file and allowing the scalar unit to access output from the scalar result unit. The output of the scalar result unit may be based on the relative magnitudes of outputs from the plurality of value processing units.

Abstract: A wireless (radio) receiver receives RF signals carrying data synchronized with a first clock. The wireless receiver demodulates the RF signals to extract the data signals and the first clock signals. The wireless receiver uses the first clock signals as write signals to write the data signals in a first-in first-out memory device (FIFO). The data signals stored in the FIFO may be read out with read signals synchronized to a second clock. In one example, a host associated with the wireless receiver reads out data signals stored in the FIFO with read signals synchronized to the system clock of the host receiver. In another example, the wireless receiver includes a data processing circuit (e.g., including forward error correction, de-whitening, and cyclical redundancy check circuits) that reads out data signals stored in the FIFO with read signals synchronized to the system clock of the wireless receiver.

Abstract: Systems and methods that cache are provided. In one example, a system may include a spatial cache system coupled to a processing unit and to a memory. The spatial cache system may be adapted to reduce the memory latency of the processing unit. The spatial cache system may be adapted to store prefetched blocks, each stored prefetched block including a plurality of cache lines. If a cache line requested by the processing unit resides in one of the stored prefetched blocks and does not reside in the processing unit, then the spatial cache system may be adapted to provide the processing unit with the requested cache line.

Abstract: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator.

Abstract: The present invention adds a plurality of substrate barriers for reducing substrate noise. The barriers, consisting of a plurality of equally sized n-well regions formed within the p-substrate, are formed between the analog and digital portions and on at least one side of sensitive analog circuits. A MOSFET transistor configured as a capacitor is formed within each of the n-well regions and is coupled between supply and circuit common to filter supply noise. A metal layer capacitor is formed above each MOSFET capacitor and is coupled between supply and circuit common. The present inventive circuit adds metallization to satisfy metal percentage requirements and to improve noise filtering. Each barrier region includes a plurality of coupled (shorted) n-wells with MOSFET transistors configured as capacitors. Additionally, in the described embodiment, the metallization layer is formed to create metal capacitors on top layers of the n-well regions to create additional noise filtering between supply and ground.

Abstract: Cancellation of interference in a communication system with application to S-CDMA. A relatively straight-forward implemented and computationally efficient approach of selecting a predetermined number of unused codes is used to perform weighted linear combination selectively with each of the input spread signals in a multiple access communication system. If desired, the predetermined number of unused codes is always the same in each implementation. Alternatively, the predetermined number of unused codes is selected from within a reordered code matrix using knowledge that is shared between the two ends of a communication system, such as between the CMs and a CMTS. While the context of an S-CDMA communication system having CMs and a CMTS is used, the solution is generally applicable to any communication system that seeks to cancel narrowband interference. Several embodiments are also described that show the generic applicability of the solution across a wide variety of systems.

Abstract: Variable code rate and signal constellation turbo trellis coded modulation (TTCM) codec. A common trellis is employed at both ends of a communication system (in an encoder and decoder) to code and decode data at different rates. The encoding employs a single TTCM encoder whose output bits may be selectively punctured to support multiple modulations (constellations and mappings) according to a rate control sequence. A single TTCM decoder is operable to decode each of the various rates at which the data is encoded by the TTCM encoder. The rate control sequence may include a number of rate controls arranged in a period that is repeated during encoding and decoding. Either one or both of the encoder and decoder may adaptively select a new rate control sequence based on operating conditions of the communication system, such as a change in signal to noise ratio (SNR).

Abstract: A method for determining beamforming coefficients begins by obtaining channel information for a multiple tone communication. The method then continues by deriving the beamforming coefficients based on the channel information and a smoothness criteria.

Abstract: A system for implementing Incremental Redundancy (IR) operations in a wireless receiver includes a baseband processor, an equalizer, a system processor, and an IR processing module. The baseband processor receives an analog signal corresponding to a data block and samples the analog signal to produce samples. The equalizer receives the samples from the baseband processor, equalizes the samples, and produces soft decision bits corresponding to the data block. The equalizer may be implemented as a distinct processing component or may be performed by the baseband processor or system processor. The system processor receives at least the soft decision bits and initiates IR operations. The IR processing module receives the soft decision bits of the data block and performs IR operations on the data block in an attempt to correctly decode a corresponding data block.