Abstract: A method and apparatus for providing local control of processing elements in a network of multiple context processing elements (MCPEs). A MCPE stores configuration memory contexts and maintains data of a current configuration. State information is received from at least one other MCPE. A configuration control signal is generated in response to the state information and current configuration data. A MCPE is selected in response to the configuration control signal to control the MCPE. Each MCPE in the networked array has an assigned physical and virtual identification. Data comprising control data, configuration data, an address mask, and a destination identification is transmitted to a MCPE. The transmitted address mask is applied to either a physical or a virtual identification, and to a destination identification. The masked physical or virtual identification is compared to the masked destination identification.

Abstract: Portable measuring devices which communicate by low power transceivers through a communication controller with a printer device collect weight and size data on articles to be shipped. The collected weight and size data are combined with origin and destination data, and labels are printed bearing pertinent shipping and routing information in machine readable format. The labels are attached to the articles to be shipped and accompany the articles to their respective destinations. At transfer points the labels are read by scanner devices which also communicate by low power transceiver links with the communication controller. The wireless linking of the scanner devices promotes human safety by the absence of cords which could cause entanglement of an operator in mechanized conveying equipment. The communication controllers at each stage of the shipping process have the capability of transferring received and updated status information on the shipped articles to a central data station.

Abstract: In a Noise Feedback Coding (NFC) system having a corresponding ZERO-STATE filter structure, the first ZERO-STATE filter structure including multiple filters, a method of producing a ZERO-STATE response error vector. The method includes: (a) transforming the first ZERO-STATE filter structure to a second ZERO-STATE filter structure including only an all-zero filter, the all-zero filter having a filter response substantially equivalent to a filter response of the ZERO-STATE filter structure including multiple filters; and (b) filtering a VQ codevector with the all-zero filter to produce the ZERO-STATE response error vector corresponding to the VQ codevector.

Abstract: A content addressable memory cell (10) comprises a word line 12, a first bit line (14), and a second bit line (16). A pair of transistors (30-31) is arranged to store bits of data at first and second points (35 and 36). A first transistor (26) is coupled to the word line, the first bit line and the first point. A second transistor (27) is coupled to the word line, the second bit line and the second point. A p-channel match transistor (40) is switchable to first and second states in response to different relationships between the stored bits and bits transmitted on the first bit line and the second bit line. A p-channel third transistor (50) couples the first bit line, first point and match transistor, and a p-channel fourth transistor (60) couples the second bit line, second point and match transistor.

Abstract: A system or apparatus for monitoring an Integrated Circuit (IC) chip includes: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals.

Abstract: An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

Abstract: A system and method for providing antialiasing of a graphical image on a display is disclosed. The graphical image is generated from data describing at least one object. The display includes a plurality of pixels. The at least one object includes a plurality of fragments. A portion of the plurality of fragments intersects a pixel of the plurality of pixels. Each of the plurality of fragments including an indication of a portion of a corresponding pixel that is intersected. The system and method include providing at least one active region for the pixel. The at least one active region intersects a first portion of the pixel. The method and system also include providing at least one new region. A first portion of the at least one new region indicates where in the pixel the at least one active region and the fragment intersect. A second portion of the at least one new region indicates where in the pixel the at least one active region and the fragment do not intersect.

Abstract: A PLL may include a voltage regulator for providing a regulated voltage to one or more PLL components (e.g. a charge pump, a voltage controlled oscillator, etc.). The PLL components may be noise sensitive components, and the regulated voltage may reduce noise received from the power supply. Additionally, a level shifter may be coupled between the PLL components and a phase/frequency detector. The level shifter may be supplied by the regulated voltage from the voltage detector. In another implementation, a PLL may include a programmable charge pump and a programmable loop filter. For example, the reference current to the charge pump may be changed, thus changing the rate at which the charge pump can change an output voltage (the control voltage to a voltage controlled oscillator in the PLL). The loop filter components may be changed to change the frequency ranges filtered by the loop filter.

Abstract: A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a way of the cache. The cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache. The state may be altered such that a succeeding cache miss causes an eviction of the particular way. Thus, a direct access transaction may be used to provide a deterministic setting to the replacement policy, providing predictability to the entry selected to store a subsequent cache miss. In one embodiment, the replacement policy may be a pseudo-random replacement policy. In one embodiment, a direct access transaction also explicitly specifies a cache storage entry to be accessed in response to the transaction.

Abstract: A method of providing for synchronizing one or more synchronous terminals with one or more synchronous endpoints, each synchronous terminal and each synchronous endpoint having an asynchronous communications network coupled between at least one synchronous terminal and at least one synchronous endpoint. A synchronization protocol is established between a synchronous terminal and a synchronous end point by providing a gateway between the asynchronous communications network and the synchronous end point, the gateway communicating with the synchronous terminal over the asynchronous communications network in accordance with the synchronization protocol. The synchronization protocol includes sending a message from the gateway to the synchronous terminal, the message containing a timestamp identifying a clock associated with the synchronous end point.

Abstract: A random number generator circuit includes a primary circuit configured to generate a value within a first range and a secondary circuit configured to generate a value within a second range. A detector circuit detects whether or not the value from the primary circuit is within the desired output range for the random number generator circuit, and selects either the value from the primary circuit or the value from the secondary circuit in response. The second range is the desired output range and the first range encompasses the second range. In one embodiment, the primary circuit has complex harmonics but may generate values outside the desired range. The secondary circuit may have less complex harmonics, but may generate values only within the desired range. In one implementation, the random number generator circuit is used to generate a replacement way for a cache.

Abstract: A lock-detect circuit is configured to detect whether an incoming signal has acquired a lock to a reference signal using a first frequency detect window and to detect whether the incoming signal has lost a previously acquired a lock to the reference signal using a second frequency detect window different from the first frequency detect window. The two signals are applied to two different down-counters that are first synchronized before initiating their count-downs. If the offset between the counts of the two counters is less than the first frequency detect window, the incoming signal is detected as having acquired a lock to the reference signal. If the offset between the counts of the two counters is greater than the second frequency detect window, the incoming signal is detected as having lost its previously acquired lock to the reference signal.

Abstract: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

Abstract: Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are capable of operating at ultra high frequencies with improved precision and noise performance. The gm cell is designed to operate on an analog input signal with a very small swing and more gradual transition edges. These characteristics allow implementation of high frequency circuits and systems including, for example, transceivers for fiber optic channels, disk driver electronics and the like.

Abstract: An amplifier assembly receives an input signal including multiple frequency channels. A first stage amplifier amplifies the input signal, to produce at an output thereof an amplified first signal including the multiple frequency channels. A plurality of second stage amplifiers have their respective inputs coupled to an output of the first stage amplifier. Each second stage amplifier amplifies the amplified first signal, to produce at its respective output a respective second amplified signal including the multiple frequency channels. The first stage amplifier and the second stage amplifiers are variable gain amplifiers, and are constructed on a common Integrated Circuit (IC) substrate.

Abstract: A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit includes a first circuit coupled to receive the clock input and a second circuit coupled to receive the clock input and the condition signal. The first circuit is configured to generate a first state on the clock output responsive to a first phase of the clock input. The second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input. In one implementation, one or more of the conditional clock buffer circuits may be included in a clock tree. The clock tree may also include one or more levels of buffering.

Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.

Abstract: A system or apparatus for monitoring an Integrated Circuit (IC) chip, comprises: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals.

Abstract: Continuously tuning a transconductance. Coupling a degeneration resistance from a first source of a first transistor in a differential pair of transistors to a second source of a second transistor in the differential pair of transistors. Applying a second variable degeneration resistance in parallel to the first degeneration resistance in response to the application of a first variable control voltage. And applying a third variable degeneration resistance in parallel to the first degeneration resistance and the second degeneration resistance in response to the application of a second variable control voltage having a fixed voltage offset from the first variable control voltage.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, graphics input and audio input simultaneously. The system includes a video decoder having a chroma-locked sample rate converter. The chroma-locked sample rate converter converts the samples to those taken at a sample rate that is a multiple of the chroma subcarrier frequency and that is locked to chroma bursts of the analog video signal in a control loop. The video decoder also includes a line-locked sample rate converter that receives samples at a multiple of the chroma subcarrier frequency and converts the samples to samples with a sample frequency that is a multiple of the horizontal line rate of the video input. The line-locked sample rate converter measures the horizontal line rate to an accuracy of a fraction of a pixel and adjusts the sample rate and phase of the line-locked sample rate converter to produce accurate line-locked samples.