Abstract: An adaptive electronic transmission signal cancellation circuit for separating transmit data from receive data in a bidirectional communication system operating in full duplex mode is disclosed. The output of a main transmitter responsive to a first bias current is connected to the output of a receiver through an internal resistor. A first replica transmitter responsive to a second bias current and matched to the main transmitter current gain and rise/fall time characteristics is connected to the input terminal of the receiver, and produces a cancellation voltage between the output terminal of the main transmitter and the input terminal of the receiver as a function of the second bias current and the internal resistor.

Abstract: A method and an apparatus for configuration of multiple context processing elements (MCPEs)are described. According to one aspect of the invention, the structure that joins the MCPE cores into a complete array in one embodiment is actually a set of several mesh-like interconnect structures. Each interconnect structure forms a network, and each network is independent in that it uses different paths, but the networks join at MCPE input switches. The network structure of one embodiment of the present invention is comprised of a local area broadcast network (level 1), a switched interconnect network (level 2), a shared bus network (level 3), and a broadcast network. In one embodiment, the level 3 network is used to carry configuration data for the MCPEs while the broadcast network is used to carry configuration data for the level 3 network drivers and switches. In one embodiment, the level 3 network is bidirectional and dynamically routable.

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract: A system may include two or more agents, at least some of which may cache data. In response to a read transaction, a caching agent may snoop its cached data and provide a response in a response phase of the transaction. Particularly, the response may include an exclusive indication used to represent both exclusive and modified states within that agent. In one embodiment, the agent responding exclusive may be responsible for providing the data for a read transaction, and may transmit an indication of which of the exclusive or modified state that agent had the data in concurrent with transmitting the data.

Abstract: The present invention relates to a method of setting a state of a one-time programmable memory device having at least one memory cell with a thin gate-ox fuse element having an oxide of about 2.5 nm thick or less using a high voltage switch. The method comprises switching in a high programming voltage into the memory cell using such high voltage switch, setting the state of the thin gate-ox fuse element.

Abstract: A signal recovery system and methods to quickly acquire signal lock and maintain consistent performance of the signal recovery system for different signal input rates of an input signal is provided. The system includes a phase locked loop system and a parameter controller. The method includes monitoring an input signal, determining a signal input rate of the input signal, providing shift factors to a loop filter contained within the signal recovery system, and adjusting the phase locked loop system performance based on the shift factors. The performance factors that can be modified include the acquisition rate, loop bandwidth, and damping factor of the phase locked loop system within the signal recovery system.

Abstract: A current mode logic (CML) flip flop includes a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch.

Abstract: The radio frequency integrated circuit (RFIC) electrostatic discharge (ESD) circuit includes a transformer balun, an impedance matching circuit and a clamping circuit. The balun is operably coupled to transpose a single-ended radio frequency (RF) signal and differential RF signal. The balun includes a 1st winding that is coupled to the single-ended radio frequency signals and a 2nd winding that is coupled for differential RF signals. The impedance matching circuit is coupled to the 1st winding and provides, in conjunction with the impedance of the balun, impedance matching with an antenna coupled to the RFIC. The clamping circuit is operably coupled to the balun and/or to the impedance matching circuit and, in combination with the impedance matching circuit and/or in combination with the balun, provides ESD protection for the receiver section and/or transmitter section of the radio frequency integrated circuit.

Abstract: A network component for processing a packet can include a rules table configured to have a plurality of entries, and sets of first storage units within each one of the plurality of entries. The sets of first storage units are configured to store sets of range checking parameters with respect to the packet. The sets of range checking parameters can identify a plurality of packet field values and a plurality of range values. In addition, the network component can include an action implementation unit configured to implement at least one first action with respect to the packet when at least one of the plurality of packet field values falls within a corresponding pair of range values for one of the plurality of entries.

Abstract: A system and method is presented for reuseing its S-CDMA related hardware (e.g., timestamp, minislot and frame count hardware) to create an extended mode to DOCSIS 2.0, namely to allow the TDMA channel to have any minislot size as is afforded to the S-CDMA channel. This reuse of existing S-CDMA hardware to create the extended mode is accomplished without the burden (e.g., complexity, cost, and schedule) of additional hardware to perform a separate set of calculations. In order to accomplish the foregoing, parameters are determined to use in a S-CDMA-type UCD message such that when that UCD message is interpreted by both the cable modem and CMTS hardware as though it were an S-CDMA message, the result is an TDMA minislot size that represents a desired integer number of ticks per minislot. In addition, the system and method periodically constructs the relationship between the system timestamp count, a channel's minislot count and the frame count via a timestamp snapshot.

Abstract: A packet switching fabric includes means forming a data ring, means forming a control ring, and means forming a plurality of data communication network links each having at least one network node coupled thereto. The fabric further includes a plurality of output queuing controlled switching devices coupled together by the data ring means and the control ring means so that the network links can be selectively communicatively coupled. Each of the output queuing controlled switching devices includes control ring processing means operative to develop, transmit and receive control messages to and from adjacent ones of the devices via the control ring means.

Abstract: A method for synchronizing counters in a terminal device, such as a cable modem in a DOCSIS-based system, with those of an administrative device, such as a headend. A cable modem advances its frame counter. With each increment of the frame counter, the cable modem's minislot counter advances by an amount equal to the number of minislots per frame. Likewise, with each increment of the frame counter, the cable modem's timestamp counter is incremented by the number of timestamps per frame. This continues until the counters at the cable modem are within one frame of the headend's counters. The minislot counter is then incremented. With each increment of the minislot counter, the timestamp counter is incremented by an amount equal to the number of timestamps per minislot. This continues until the cable modem's counters are within a minislot of the headend's counters. The timestamp counter is then incremented until the cable modem's counters match those of the headend.

Abstract: A differential linear fractional N-synthesizer includes a phase and frequency detection module, a linearized charge pump, a low pass filter, a voltage controlled oscillator, and a fractional N divider feedback. The phase and frequency detection module is operably coupled to produce a differential charge-up signal, a differential charge-down signal, or a differential off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The feedback oscillation is generated by the fractional N divider feedback, which divides an output oscillation by a divider value to produce the feedback oscillation. The linearized charge pump includes a 1st current source, a 2nd current source and a modulation module. In response to the differential off signal, the modulation module produces a modulated differential off signal that causes the 1st and 2nd current sources to produce a zero current signal in an alternating fashion.

Abstract: A method and system for providing a graphical image on a display of a system is disclosed. The graphical image is provided from data describing a plurality of primitives. The display includes a plurality of pixels. The method and system include providing a plurality of variable-sized bins containing the plurality of primitives and rendering the plurality of primitives by rendering each of the plurality of variable-sized bins variable-sized bin by variable-sized bin.

Abstract: A system for reducing the complexity of an adaptive decision feedback equalizer, for use in connection with a dual-mode QAM/VSB receiver system is disclosed. QAM and VSB symbols, which are expressed in two's compliment notation, include an extra bit required to compensate for a fixed offset term introduced by the two's compliment numbering system. A decision feedback equalizer includes a decision feedback filter section which operates on symbolic decisions represented by a wordlength which excludes the added bit representing the offset. The vestigal word is convolved with the decision feedback filter's coefficients, while a DC component, corresponding to the excluded bit, is convolved with the same coefficient values in a correction filter. The two values are summed to provide an ISI compensation signal at the input of a decision device such as a slicer. A DC component representing a pilot tone in VSB transmission systems also introduces a DC component, and additional bits, to a VSB wordlength.

Abstract: An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hystersis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals.

Abstract: A method for decoding a word received at a current time instant into a symbol of a trellis code. The trellis code corresponds to a trellis diagram having N states associated with the current time instant. Each of the N states corresponds to at least one incoming branch. Each of the incoming branches is associated with a symbol of the trellis code. The branch metrics are computed for the incoming branches such that a branch metric represents a distance between the received word and a symbol associated with the corresponding branch. The branch metric is represented by fewer bits than a squared Euclidian metric representation of the distance. For each of the N states, a node metric is computed based on corresponding branch metrics and one of the incoming branches associated with the state is selected. One of the N states is selected as an optimal state based on the node metrics. The symbol associated with the selected incoming branch corresponding to the optimal state is the decoded word.

Abstract: Methods and apparatus are provided for making function calls to various cryptography accelerators. An application program interface abstraction layer coupled to a cryptography accelerator receives generic function calls from designer configured software and performs operations such as security association management, policy management, packet processing, cryptography accelerator configuration, and key commit management. Upon receiving a generic function call, the abstraction layer performs processing to make a chip specific function call or update abstraction layer management information associated with the generic function call.

Abstract: A voltage regulator may include one or more features for generating high PSRR. For example, source follower devices may be included in the voltage regulator for providing current sources for the output voltage nodes. The source followers may be sensitive to power supply noise at the gate terminal. Filters are included on the gate terminals to filter the power supply noise, thus reducing the noise at the gate terminals. As another example, the voltage regulator may employ current sources on the output voltage nodes which produce current inversely proportional to the current drawn by the load. In one embodiment, the voltage regulator may include a power control circuit used to provide overvoltage protection during power up. The power control circuit provides a voltage during power up, and ceases providing the voltage after a time interval so that the circuit may operate.

Abstract: A static latch can be converted to a dynamic latch by closing a pair of switches. When the switches are open, a first pair of back-to-back transistors serves as the static latch. When the switches are closed, a second pair of back-to-back transistors is connected to the first pair so the two pairs acting together serve as a dynamic latch.