Abstract: An integrated oscillator that may be used as a time clock includes circuitry that oscillates about an RC time constant, which RC time constant is adjustable to provide a desired frequency of oscillation. More specifically, the oscillator includes a capacitor array that has a plurality of capacitors coupled in parallel wherein each capacitor may be selectively included into the RC time constant or selectively excluded there from. Rather than setting the capacitance values to a desired capacitance value, a system for adjusting the time constant includes circuitry for measuring an output frequency and for comparing that to a certified frequency source wherein the time constant is adjusted by adding or removing capacitors from the capacitor array until the frequency of the internal clock matches an expected frequency.

Abstract: A method is provided of processing data representing pixel colour having a luminance component and colour difference components. The data is divided into first and second data portions, the first data portion comprising the luminance components and the second data portion comprising the colour difference components. First and second instructions from a combined instruction word, and the first and second date portions are processed in parallel using first and second parallel processors within a processor architecture, the first and second parallel processors operating according to the first and second instructions, respectively. The processed first and second data portions are combined to provide processed pixel colour data. This method uses parallel processor sections to process the luminance and colour difference components. The parallel processor sections can then use instructions suited to the type of data being processed, providing an efficient method of processing the graphics data.

Abstract: The present invention is a metal bond pad that provides electrical and mechanical connection to an integrated circuit (IC). The metal bond pad is configured to accommodate for probe travel during probing measurements, without modifying the size of the passivation opening of the bond pad. This enables higher density of active devices on the IC and therefore increases integration and lowers IC cost. The metal bond pad for the integrated circuit includes a substrate, a first metal layer, and a second metal layer. The substrate has the first metal layer disposed therein, having an opening from the top surface of the substrate. The second metal layer has a first-end portion, a second-end portion and a center portion disposed between the first-end portion and the second-end portion. The center portion of the second metal layer is aligned with the opening in the substrate and a bottom surface of the center portion is in contact with the top surface of the first metal layer.

Abstract: A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively with each of two or more packed objects in an offset register.

Abstract: A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data.

Abstract: Often programmable gain attenuators (PGAs) are combined with high pass filters. Adjustment of the highpass filter however can have unintended effects, such as changing the step size of the PGA. By placing the resistance of the highpass filter in parallel with a programmable attenuator divider, the steps of the PGA can be minimally affected as the highpass frequency is adjusted.

Abstract: A method and system for processing textures for a graphical image on a display is disclosed. The graphical image includes an object. The object includes a plurality of fragments. The method and system include providing a memory and providing a plurality of texture processors coupled with the memory. The memory is for storing a portion of a program for processing a plurality of textures for the plurality of fragments. Each of the plurality of texture processors is for processing a texture for a fragment in accordance with the program. The plurality of texture processors is capable of processing a part of the plurality of textures in parallel.

Abstract: A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, a graphics input and an audio input simultaneously. The chip uses window descriptors to describe logical surfaces, or windows, of graphics information to be displayed on the screen. The chip incorporates a unified memory architecture that provides a high level of system performance while conserving memory bandwidth and chip size. Video and graphics scaling capabilities as well as anti-flutter filtering capability are provided.

Abstract: Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow.

Abstract: The present invention provides a method for determining nonlinear distortion of a transmitter. A test symbol sequence is transmitted from the transmitter under test as an analog output signal. The analog output signal is sampled to produce a first sequence which represents the test symbol sequence as distorted by a linear distortion sequence and a nonlinear distortion sequence. The test symbol sequence is filtered via an adaptive filter to produce a second sequence such that the second sequence is approximately equal to the test symbol sequence as distorted by the linear distortion sequence. The second sequence is subtracted from the first sequence to produce an output sequence substantially equal to the nonlinear distortion sequence.

Abstract: Improved carrier recovery, symbol timing, and carrier phase tracking systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system are disclosed. Carrier and phase recovery systems operate on complex signals representing symbols having the same time stamp for each phase error term. in-phase signals are sampled twice a symbol at the in-phase symbol sampling time and at the quadrature-phase symbol sampling time. The signals are de-multiplexed to generate I and XI data streams, where I represents the in-phase sampling time signals and XI represents mid-symbol point sample times. A similar procedure is carrier out on quadrature-phase signals. When the in-phase signal is de-multiplexed to generate a symbol I, the quadrature-phase signal is de-multiplexed to generate its mid-symbol point XQ. Both I and Q are decoded in a decision device to define a symbol error term, which is combined with the opposite mid-symbol signal to define a phase error term PI and PQ for each rail.

Abstract: A circuit for applying power to mixed mode integrated circuits in a predefined sequence. The circuit includes a first circuit powered by a first voltage and a second circuit powered by a second voltage that is less than the first voltage and having the second voltage coupled to the first circuit. The circuit for applying power to mixed mode integrated circuits includes[[,]] a modified [[IO]] I/O cell of the second circuit. The modified [[IO]] I/O cell has a driver transistor including a back gate terminal, a gate terminal that is driven by the second circuit, a source drain terminal that is coupled to a first circuit signal, and a drain source terminal that is coupled to the second power supply voltage. The circuit for applying power to mixed mode integrated circuits further includes[[,]] a controller circuit coupled to the first voltage and the second voltage supplied as controller circuit inputs.

Abstract: A system for servicing data transactions within a processing device using common data paths. The system is broadly comprised of: a plurality of source agents operable to transmit a plurality of data cells; a plurality of destination agents operable to of data cells; a plurality of virtual channels for transporting data cells between the source agents and the destination agents; and a switch. The switch is operable to connect predetermined combinations of the source agents and the destination agents for the transmission of data. The switch generates a plurality of switch processing cycles and processes a plurality of control signals during the switch processing cycles.

Abstract: An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a channel under test. A packet receive circuit includes a second memory for storing received packet data and is connectable to the channel under test. An interface is used for programming the packet transmit and packet receive circuits. The packet transmit circuit can generate an arbitrary 10G SERDES packet in response to commands from the interface. The packet receive circuit can determine a bit error rate of the channel under test. The second memory can capture received packet data upon any one of (a) after a pre-programmed pattern is detected, (b) after a pre-programmed pattern is lost, and (c) after an error is detected.

Abstract: An analog to digital converter includes a first amplifier array connected to taps from a reference ladder, a second amplifier array, wherein each amplifier in the first amplifier array is connected to only two amplifiers of the second amplifier array, a third amplifier array, wherein each amplifier in the second amplifier array is connected to only two amplifiers of the third amplifier array, and an encoder connected to outputs of the third amplifier array that converts the outputs to an N-bit digital signal.

Abstract: Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

Abstract: A power supply and switching technique is provided that utilizes a first battery and a second battery to charge a load. The power supply includes a first controlled power switch coupled to the first battery and the load, a second controlled power switch coupled to the second battery and the load, and a power controller coupled to the first controlled power switch, the second controlled power switch, and the load. The power controller monitors the voltage and the load and causes a charge to be applied to the load when the load voltage is not a predetermined voltage. The power controller causes a charge to be applied to the load by selectively closing the first controlled power switch, thereby providing a charge from the first battery to the load, and/or selectively closing the second controlled power switch, thereby providing a charge from the second battery to the load. A similar switching technique may be used to recharge the first and second battery by alternately coupling them to an external power source.

Abstract: An SRAM cell eliminates the p-channel pull-up resistors to decrease its physical size. A tracking circuit generates a control signal used to ensure that the memory state is preserved during the idle state. The control signal controls the wordline voltage during the idle state to vary the leakage through the access transistors to ensure that current into the node through the access device is not exceeded by leakage current out of the output nodes through the storage devices. The tracking circuit control signal can also be used to vary the well to substrate bias voltage of the storage devices to decrease the leakage through the storage devices. The control signal can also be used to bias the supply rail voltage to which the storage devices are directly coupled to decrease the amount of leakage through the storage devices.

Abstract: A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

Abstract: An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing any of the other signals of the band. An input frequency band such as a television channel spectrum is initially demodulated to baseband and applied to the input of the filter. The baseband spectrum is combined in a complex mixer with a synthesized frequency signal that shifts the spectrum a characteristic amount, in the frequency domain, so as to position an interference component in the region about DC. Once shifted, the frequency components about DC are removed by DC canceler circuit and the resulting spectrum is mixed with a subsequent synthesized frequency signal which shifts the spectrum back to its original representation and baseband. The frequency signals are developed by a programmable frequency synthesizer which a user may program with an intelligence signal that defines the frequency location of an interference signal within the spectrum.