Abstract: A source-follower transistor based buffer provides high linearity. A replica transistor is used to generate a replica voltage substantially equal to the output voltage of the buffer. The replica voltage is level shifted by a level shift circuit and applied at the drain of the source-follower transistor to improve the linearity of the buffer. The buffer may be used in conjunction with a switched-capacitor sampling circuit. A damping circuit may be used to reduce charge glitches due to sampling. The damping circuit may be a low pass filter. The buffer may be used in an interface circuit that produces an output signal from an input signal and controls the level of the output signal.

Abstract: A system for servicing data transactions within a processing device using common data paths. The system is broadly comprised of: a plurality of source agents operable to transmit a plurality of data cells; a plurality of destination agents operable to receive a plurality of data cells; a plurality of virtual channels for transporting the data cells between the source agents and the destination agents; and a switch for connecting selected pairs of source agents and destination agents for transmission of data over predetermined virtual channels.

Abstract: A programmable divider includes a synchronous counter configured to process an input clock signal and produce first output signals in response the input clock signal. A number of logic devices are coupled to the synchronous counter and configurable to receive the first output signals and correspondingly produce second output signals. Also included is a multiplexer that is configured to receive the second output signals and has an output coupled to an input of the synchronous counter. In the programmable divider, characteristics of the synchronous counter are selectable based upon a particular number of the logic devices configured.

Abstract: A supervisory communications system (such as, a headend cable modem termination system) manages communications with a plurality of remote communications devices (such as, a cable modem). The supervisory system enables each of its physical channels to have multiple logical channels, with each logical channel having differing channel parameters or operating characteristics. As a result, different types of communication devices are permitted to coexist on the same physical spectrum. In other words, a communications device using, for example, spread spectrum modulation technologies require different operating characteristics than a communications device using, for example, time division multiplexing technologies.

Abstract: A method and device for testing multi-channel transceivers in an integrated circuit is provided. More specifically, the present invention relates to a method and device for implementing a built-in self-test for multi-channel transceivers. An exemplaxy embodiment of the present invention includes a test pattern generator, a multiplexer, a demultiplexer, and a test result evaluator. The test pattern generator generates a test pattern which is fed into each of the input channels of the multiplexer. The multiplexer multiplexes the data from all its input channels and then relays the data to the demultiplexer. The test result evaluator then individually checks the data at each of the output channels of the demultiplexer to determine whether the data received at each output channel is the same as the test pattern. In order to facilitate the checking process, signature analysis is utilized.

Abstract: Systems and methods for digital upconversion of baseband television signals that can be used in cable television headend systems are provided. In one embodiment, the system includes a digital frequency adjustment system and a digital to analog conversion system. In a feature of the embodiment, the digital frequency adjustment system consists of set of digital upconversion and upsample elements that shift upwards the frequency of baseband signals. In a further feature of the embodiment, a tree structure of sets of upsample and upconversion elements is used. In another embodiment, the system includes digital and analog frequency adjustment systems in which the frequencies of the input signals are partially upshifted within both the digital and analog domains. Methods for digital upconversion of television signals are also provided.

Abstract: A decoder providing asynchronous reset, redundancy, or both an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

Abstract: An integrated receiver with dual channel transport stream decoding and delivery substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides multiple time-base clocks for two transport streams. Transport processor circuitry uses multiple PCRs to track transport streams through decoding, storage and or delivery of the decoded signals for display. Provision of a multiple time-base clock for decoding and delivering multiple transport streams allows display of the two de coded audio-video signals on independent monitors.

Abstract: A system for transmitting subchannel data over the same media as high speed data, especially DC balanced high speed data. A digital transmitter receives subchannel data and modulates it onto a subchannel carrier as the host signal in the preferred embodiment using frequency shift keying. The FSK subchannel carrier is added by superposition to the high speed data signal. At the receiver, a low pass filter filters out the subchannel carrier frequency components which are then amplified and subjected to a two-pole anti-aliasing filter to remove the third and fifth harmonics. Analog-to-digital conversion is followed by a digital mix down to remove the subchannel carrier component using a local oscillator at the subchannel carrier frequency. An FIR low pass filter having a triangular time domain response performs anti-aliasing and leaves as an output only frequency components at the positive and negative deviation frequency for Mark and Space.

Abstract: A process of generating an inter-packet gap in a network device is disclosed. First, it is determined whether a next packet is available to forward from a packet buffer. The number of tokens contained in a token bucket is checked and bytes are added to the inter-packet gap and tokens are added to the token bucket, when the number of tokens contained in a token bucket is less than a predetermined number of tokens. Otherwise, the size of the inter-packet gap is reduced and tokens are taken out of the token bucket, when the number of tokens contained in a token bucket is greater than or equal to the predetermined number of tokens. Thereafter, the inter-packet gap is supplied and sent with the next packet over an interface between the network device and a network.

Abstract: A high speed data link includes transmitter equalization and (passive) receiver equalization to compensate for frequency distortion of the data link. In one embodiment, the transmitter equalization is performed with a de-emphasis circuit. The transmitter de-emphasis circuit pre-distorts an input signal to compensate for at least some of the frequency distortion in the data caused by the transmission line. The (passive) receive equalization circuit further compensates for the frequency distortion at the output of the transmission line to flatten the amplitude response of the output signal, and thereby reduce inter-symbol interference, improve media reach and improve the bit error rate (BER).

Abstract: The network device includes a transceiver, a pattern generation unit and a pattern recognition unit. The transceiver connects to a communications medium. The pattern generation unit connects to the transceiver. The pattern generation unit is configured to generate a first code word in response to a self-test signal. The pattern recognition unit connects to the communications medium and a network entity. The pattern recognition unit is configured to receive the first code word from the transceiver and to determine whether the first code word includes a loop back pattern. The pattern recognition unit is configured to generate a second code based upon the first code word and to include in the second code word a pattern different from the first code word.

Abstract: A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in a set of symbols. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

Abstract: An active termination for a transmission line comprising a reference impedance, a terminating impedance and a control circuit. The reference and terminating impedances are identical circuits made on the same integrated circuit in close proximity to one another. Both impedances are made of an active and a passive resistor in series. The active resistor is a CMOS transistor operated as a voltage controlled resistor. A control circuit senses the impedance of the reference impedance and generates a control signal to change the impedance of the reference and terminating impedances such that they are made equal to the impedance of the transmission line. An alternate embodiment of the invention comprises an active resistor and a passive resistor in series to form a terminating impedance network. A control circuit senses the voltage on the transmission line and adjusts the active resistor to terminate the transmission line with the correct value of resistance.

Abstract: A graphics display system integrated circuit is used in a set-top box for controlling a television display. The graphics display system processes analog video input, digital video input, and graphics input. The system incorporates a unified memory architecture that is shared by the graphics system, a CPU, and other peripherals. The unified memory architecture uses real time scheduling to service tasks. Critical instant analysis is used to find a schedule for memory usage that does not affect memory requirements of real time tasks while at the same time servicing non-real-time tasks as needed.

Abstract: The present invention relates to a replica network for linearizing switched capacitor circuits. A bridge circuit with a MOSFET resistor disposed in a resistor branch of the bridge circuit is provided. A noninverting terminal of an operational amplifier is connected to a first node of the bridge circuit and an inverting terminal of the operational amplifier is connected to a second node of the bridge circuit. The second node is separated from the first node by another node of the bridge circuit. An output of the operational amplifier is provided to a gate terminal of the MOSFET resistor and to the gate terminal of the MOSFET switch in a switched capacitor circuit, thereby controlling the resistance of the MOSFET switch so that it is independent of the signal voltage. In this manner, the replica network of the present invention linearizes the switched capacitor circuit. In this manner, the replica network of the present invention linearizes the switched capacitor circuit.

Abstract: A method of decompressing data words of an instruction set includes: A. filling a primary dictionary with at least one primary data word of the instruction set, each of the at least one primary data word being stored in the primary dictionary in a location associated with a distinct primary dictionary index; B. filling at least one secondary dictionary with at least one difference bit stream, each of the at least one difference bit stream being stored in one of the at least one secondary dictionary in a location associated with a distinct secondary dictionary index; C. receiving a code word, the code word comprising: a. a header which identifies the primary dictionary and a specific one of the at least one secondary dictionary; b. a first bit stream; and c. a second bit stream; wherein the first bit stream comprises the distinct primary dictionary index and the second bit stream comprises the distinct secondary dictionary index; D.

Abstract: A differential line driver includes first, second, third and fourth cascode transistors connected in parallel, wherein drains of the first and third transistors are connected to a negative output of the differential line driver, and wherein drains of the second and fourth transistors are connected to a positive output of the differential line driver. First, second, third and fourth switching transistors are connected in series with corresponding first, second, third and fourth cascode transistors and driven by a data signal. First and second compound transistors inputting a class AB operation signal at their gates, wherein the first compound transistor is connected to sources of the first and second switching transistors, and wherein the second compound transistor is connected to sources of the third and fourth switching transistors.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequencing problems provide an interim voltages during power-on sequences in order to prevent over-voltage conditions across IC terminals. Voltages at first and second terminals of a circuit are monitored and an interim voltage to the second terminal is provided when the voltage at the first terminal exceeds a first threshold and a voltage at the second terminal is below a second threshold. The interim voltage protects the circuit from excessive voltage differences across the first and second terminals during power-on sequences, and is deactivated during normal operation so as not to draw excessive current. The method/system helps to insure that multi-supply dependent logic and/or other circuitry does not receive inappropriate voltage levels, and thus helps to insure that lower voltage level based circuitry is not damaged during power-up, transients, and/or glitches.

Abstract: The present invention relates in general to integrated circuits, and in particular to method and circuitry for implementing an improved phase-locked loop (PLL) in complementary metal-oxide-semiconductor (CMOS) technology using current-controlled CMOS (C3MOS) logic. In an exemplary embodiment, a phase-locked loop includes a phase-frequency detector, a Gm cell block, a low pass filter and a voltage controlled oscillator. These various elements of the phase-locked loop are connected to one another in a fully differential manner, i.e., each element has an input and/or an output each having at least a differential signal. In one embodiment, each of these various elements of the phase-locked loop is implemented using C3MOS logic.