Abstract: A filter structure used with a dynamic element matching encoder for a sigma-delta digital-to-analog converter is presented. A sampled input sequence having undesired frequency tones is divided into even and odd data sub-sequences. Each of the sub-sequences is processed by a dynamic element matching encoder, with a transfer function H(z−1). The resulting processed sub-sequences are combined into an output sequence. The undesired frequency tones are substantially reduced in the output sequence.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequencing problems provide an interim voltages during power-on sequences in order to prevent over-voltage conditions across IC terminals. Voltages at first and second terminals of a circuit are monitored and an interim voltage to the second terminal is provided when the voltage at the first terminal exceeds a first threshold and a voltage at the second terminal is below a second threshold. The interim voltage protects the circuit from excessive voltage differences across the first and second terminals during power-on sequences, and is deactivated during normal operation so as not to draw excessive current. The method/system helps to insure that multi-supply dependent logic and/or other circuitry does not receive inappropriate voltage levels, and thus helps to insure that lower voltage level based circuitry is not damaged during power-up, transients, and/or glitches.

Abstract: There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said plurality of bits with at least one of said plurality of bits supplied via a unitary operator, the unitary operator being effective to selectively alter the logical value of said bit depending on its logical value in the first register address, and using said second register address to access said register file. A computer system for carrying out such a technique is also enclosed.

Abstract: A ring oscillator circuit, such as a VCO, with a relatively high level of noise rejection for noise originating from both the voltage supply and ground. The ring oscillator circuit is composed of a plurality of differential delay circuits, each differential delay circuit generating a differential output signal that is a delayed (and preferably inverted) version of a differential input signal. ‘Each differential delay circuit includes first and second input transistors for receiving the differential input signal. Each differential delay circuit also includes first and second load transistors coupled in parallel with the respective first and second input transistors. Each differential delay circuit further includes a first current source coupled between the first input transistor and a first power supply terminal (e.g.

Abstract: A low voltage current mirror circuit (also referred to as a bias circuit) for establishing a plurality of bias voltages from an input current supplied to an input terminal of the circuit includes an input stage, a current stage connected to the input stage, a feedback stage connected to the current stage, a reference bias stage connected to the feedback stage and the current stage. The circuit establishes first and second bias voltages suitable for biasing current sources of a first type, and third and fourth bias voltages suitable for biasing current sources of a second type complementary to the first type. The bias voltages track the input current over variations in at least one of process, temperature and power supply voltage.

Abstract: Methods and systems for improved feedback processing in delta-sigma modulators, including single bit and multi-bit delta-sigma modulators, continuous-time and discrete-time delta-sigma modulators, and digital and/or analog feedback loops. One or more processes are performed in a pipeline having a higher throughput rate than a throughput rate of a delta-sigma modulator. Any of a variety of processes and combinations of processes can be performed in the pipeline including, without limitation, quantization, digital signal processing, and/or feedback digital-to-analog conversion.

Abstract: The present invention generally relates to voltage-controlled oscillators. More specifically, the present invention relates to method and circuitry for implementing a differentially tuned varactor-inductor oscillator. In one exemplary embodiment, the present invention includes an LC tank circuit having a couple of terminals, a first and second capacitors, and a first and second varactors. The first and second varactors are connected in series forming a first and a second node. The first capacitor connects the first node and one terminal of the LC tank circuit. The second capacitor connects the second node and the other terminal of the LC tank circuit. A pair of differential input control signals is applied across the first and the second varactors, respectively, to tune the LC tank circuit thereby generating an oscillator output.

Abstract: A process of controlling a flow of data in a wireless network providing wireless access to the wireless network by wireless devices is disclosed. Data is received from a wireless device by a network device, through one access point of a plurality of access points in communication with the network device, indicating a client identifier for the wireless device. The client identifier is forwarded to an authentication server and the network device mediated authentication of the wireless device with the authentication server. Thereafter, data packets received from portions of the wireless network and from the plurality of access points are evaluated and the received data packets are passed to portions of the wireless network and to the plurality of access points, based on the evaluation of the received data packets. In addition, the network device periodically polls for a status of the wireless device from the access point.

Abstract: A network device for processing a packet can include an ingress port configured to receive the packet. In addition, the network device can include a membership port bit map table configured to store at least one membership port bit map, an outgoing port bit map table configured to store at least one outgoing port bit map. A first storage unit within the network device can be configured to store an egress port bit map. The egress port bit map is based on the membership port bit map and the outgoing port bit map. Furthermore, the network device can have at least one egress port configured to transmit out the packet. The at least one egress port can correspond to the egress port bit map.

Abstract: A network component for processing a packet can include a buffer configured to receive a packet in an ingress port at a network component, a first identification unit configured to identify a destination address and a network identifier from the packet received at the buffer, and a look-up table configured to be indexed by the destination address and the network identifier identified by the identification unit to obtain an outgoing port bit map. In addition, the network component can include a forwarding unit configured to forward the packet to a destination module and out of an egress port within the network component based on the outgoing port bit map.

Abstract: A method and apparatus for improving the performance of a superscalar, superpipelined processor by identifying and processing instructions for performing addressing operations is provided. The invention heuristically determines instructions likely to perform addressing operations and assigns those instructions to specialized pipes in a pipeline structure. The invention can assign such instructions to both an execute pipe and a load/store pipe to avoid the occurrence of “bubbles” in the event execution of the instruction requires the calculation capability of the execute pipe. The invention can also examine a sequence of instructions to identify an instruction for performing a calculation where the result of the calculation is used by a succeeding load or store instruction. In this case, the invention controls the pipeline to assure the result of the calculation is available for the succeeding load or store instruction even if both instructions are being processed concurrently.

Abstract: An apparatus is disclosed which includes a converter circuit and a noise suppression circuit. The converter circuit has a dynamic logic input, and is configured to generate a static logic output on an output node responsive to the dynamic logic input. The noise suppression circuit is coupled to receive a clock signal and is coupled to the output node. Responsive to a first phase of the clock signal, a precharge of a dynamic logic circuit generating the dynamic logic input occurs. The noise suppression circuit is configured to actively drive the static logic output on the output node responsive to the first phase. In some embodiments, the noise suppression circuit may reduce the noise sensitivity of the static logic output during the precharge phase, and may not impede operation of the converter circuit during the evaluate phase.

Abstract: A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

Abstract: A network device includes a network port, at least one register, and a network information receiver. The network port is configured to send and receive data packets. The at least one register contains configuration data related to the network port. The network information receiver is coupled with the network port and is configured to receive the data packet from the network port, extract low level data from the data packet, and update the at least one register based on the low level data.

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract: A portable data terminal includes at least two communication transceivers having different operating characteristics, one for conducting data communications on a wired subnetwork and one for conducting data communications on a wireless subnetwork. A communication processor converts data received by the communication transceivers to a predetermined format for a base module and converts data in a predetermined format from the base module to a format for transmission by a selected one of the first and second communication transceivers, thereby isolating the base module from differing characteristics of the transceivers. The communication processor is arranged to relay communications received by one transceiver for re-transmission by the other transceiver and to transfer communications from one subnetwork to the other, without activating the base module.

Abstract: Carrier signals are modulated by information (e.g., television) signals in a particular frequency range. The information signals are oversampled at a first frequency greater than any of the frequencies in the particular frequency range to provide digital signals at a second frequency. The digital signals are introduced to a carrier recovery loop which provides a feedback to regulate the frequency of the digital signals at the second frequency. The digital signals are introduced to a symbol recovery loop which provides a feedback to maintain the time for the production of the digital signals in the middle of the data signals. The gain of the digital signals is also regulated in a feedback loop. The digital signals are processed to recover the data in the data signals. By providing digital feedbacks, the information recovered from the digital signals can be quite precise. In one embodiment, the carrier signals are demodulated to produce baseband inphase and quadrature signals.

Abstract: A circuit and a method for limiting a voltage to a specified value (e.g., a rail voltage) without clipping thereby includes a pair of MOSFETs that turn on when a specified bias voltage is reached to either add to or sink current from the input node of the resistive load responsive to fluctuations in current going through the output resistive load to maintain a constant current through it. A plurality of biasing circuits is provided that control the turn on voltage levels for the MOSFETs to achieve the desired operation. The biasing circuits include circuit components that are matched to circuit components within the circuitry that adds and drains current to the output resistive load including a resistive load that matches the output resistive load.

Abstract: Binary indications are converted to an analog representation with significant reduction in ringing at the transitions between successive binary indications and in the period during each binary indication. The binary indications are disposed in a row-and-column matrix to provide a thermometer code. Each stage of the converter includes a decoder and latch arranged so the decoder inputs settle before the latch is set by the clock pulses. The stages are implemented in complementary CMOS. Complementary transistors are biased so one transistor of the pair is driven to the rail while the other transistor of the pair floats. A dummy CMOS transistor is used to balance the number of transistors in the decoder paths.

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.