Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes: a substrate having a bit line extending along a first direction; a semiconductor channel located on the bit line; a semiconductor doping layer located on the side of the bit line, wherein the top surface of the semiconductor doping layer is connected to the semiconductor channel contact; a word line extending in the second direction, encircling part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line; a word line dielectric layer located between the word line and the semiconductor channel; an isolation layer located between the word line and the bit line and between the word line and the semiconductor doping layer. The device and method improve the prior weak electrical conductivity between the bit line structure and the active structure.

Abstract: A semiconductor structure includes a chip structure and a sealing structure disposed on a substrate of the semiconductor structure. The sealing structure includes a metal wall body and a blocking wall body located on a top of the metal wall body, and the metal wall body and the blocking wall body both are disposed around the chip structure.

Abstract: The present disclosure relates to a fixture, the fixture is a fixture for a semiconductor etching machine, and the fixture includes: a support mechanism, configured to be arranged on an outer base of an electrostatic chuck of the semiconductor etching machine; a cleaning mechanism, being rotatably arranged on the support mechanism; and at least one cleaning unit, being arranged on the cleaning mechanism.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a semiconductor base, a bit line and a word line. The semiconductor base includes a substrate and an isolation structure. The isolation structure is arranged above the substrate and configured to isolate a plurality of active regions from each other. The bit line is arranged in the substrate and connected to the plurality of active regions. The word line is arranged in the isolation structure, intersects with the plurality of active regions and surrounds the plurality of active regions. The substrate is a Silicon-On-Insulator (SOI) substrate.

Abstract: A sense amplifier circuit, memory device and related operation methods are provided. The sense amplifier circuit includes an amplification circuit for amplifying a voltage signal and a compensation circuit coupled to the amplification circuit. The amplification circuit includes a first inverting amplifier and a second inverting amplifier cross-coupled with each other, with the first inverting amplifier connected to a first bitline and the second inverting amplifier connected to a second bitline. The compensation circuit includes a first, a second, a third, and a fourth switch circuits, and is configured to generate a compensation voltage between the first bitline and the second bitline by conducting charge injections through operating the switch circuits to compensate an input-referred offset voltage of the amplification circuit.

Abstract: A power supply circuit and a memory are provided. The power supply circuit includes: a voltage generation module, configured to provide an initial voltage signal; a first power supply module, configured to provide a power reference voltage based on the initial voltage signal; an amplification module, configured to generate and output a first power voltage based on the power reference voltage; a first power network, configured to supply power to at least one function module connected to the first power network; a second power supply module, a second power network and a voltage control module. The second power supply module is configured to provide a second power voltage for the second power network based on the initial voltage signal.

Abstract: Embodiments provide a command processing circuit and a data processing circuit, including a plurality of flip-flops. An output terminal of a former flip-flop is connected to an input terminal of a latter flip-flop. The flip-flop is configured to sample, according to switching of a data strobe signal, an internal write command inputted into the command processing circuit to obtain a sampling command, to sample data. An output terminal of a target flip-flop is connected to a target terminal of a first flip-flop, the target flip-flop is a flip-flop whose time of outputting an active level overlaps target time, where the target time is start time and/or end time of a pulse in the internal write command. The target flip-flop is configured to reset the internal write command in the first flip-flop by outputting the active level.

Abstract: An overhead buffer double-entry detection system, which includes an overhead hoist transport, a first sensing unit for scanning and generating detection data of a horizontal range, a driving device for moving the first sensing unit in a vertical range, a controlling unit, and an overhead hoist transport controlling system for sending a detection instruction and a driving instruction to the controlling unit when the overhead hoist transport moves to a corresponding overhead buffer position, whereby the controlling unit bases on the driving instruction to control the driving device to move the first sensing unit in a vertical range, bases on the detection instruction to control the first sensing unit to scan and generate detection data of each horizontal range within the overhead buffer during movement process, and bases on the detection data of each horizontal range within the overhead buffer to judge whether there is obstacle in the overhead buffer.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method includes: providing a substrate including a core NMOS area, a core PMOS area and a peripheral NMOS area; performing oxidation treatment on the substrate in the core PMOS area to convert a thickness of a part of the substrate in the core PMOS area into an oxide layer; removing the oxide layer; forming a first semiconductor layer on the remaining substrate in the core PMOS area; forming a gate dielectric layer located on the first semiconductor layer and on the substrate in the core NMOS area and the peripheral NMOS area; and forming a gate on the gate dielectric layer.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a vacuum system, a low-pressure vacuum process device, and a cutoff member. The vacuum system includes: a vacuum pump; an exhaust pipeline, wherein one end of the exhaust pipeline is used to communicate with a chamber to be evacuated, and the other end of the exhaust pipeline communicates with the vacuum pump; and a cutoff member, wherein the cutoff member is connected to the exhaust pipeline, the cutoff member includes a filter portion and a carrier portion, the filter portion includes a passage, the carrier portion includes an accommodation groove, and the passage communicates with the accommodation groove.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a substrate, bit line structures and isolation walls located on side walls of the bit line structures, and capacitor contact holes. In the substrate, conductive contact regions are arranged. The conductive contact regions are exposed from the substrate. A plurality of discrete bit line structures are located on the substrate. Each of the isolation walls includes at least one isolation layer and a gap between the isolation layer and the bit line structure. Each of the capacitor contact holes is constituted by a region surrounded by the isolation walls between the adjacent bit line structures. The capacitor contact holes expose the conductive contact regions. A top width of the capacitor contact holes is larger than a bottom width thereof in a direction parallel to an arrangement direction of the bit line structures.

Abstract: An injection mould and an injection moulding method are provided. The injection mould includes: a base plate, configured to place a package chip to be injection-moulded, the package chip including a substrate and at least one chip fixed on a surface of the substrate by a flip chip process, the substrate having a through hole, a glue injection channel being formed in the base plate and configured to inject a moulding compound, and the glue injection channel being connected with the through hole on the substrate. The above-mentioned injection mould can improve the reliability of the package chip after injection moulding.

Abstract: The present application provides a semiconductor structure and a forming method thereof. The method of forming the semiconductor structure includes: providing a semiconductor chip and a substrate; forming, on the substrate, a first covering film covering a metal pad and a surface of the substrate, a plurality of up-narrow and down-wide openings being formed in the first covering film, and a bottom of each of the up-narrow and down-wide openings correspondingly exposing a surface of the metal pad; and flipping the semiconductor chip onto the substrate, such that a solder bump on a metal pillar is correspondingly located in the up-narrow and down-wide opening, and the solder bump fill the up-narrow and down-wide opening.

Abstract: A method for forming a semiconductor structure and the semiconductor structure are provided. The method for forming the semiconductor structure includes: providing a substrate, wherein a separate bit line structure is formed on the substrate; forming a first sacrificial layer on the side wall of the bit line structure; forming a first dielectric layer filling gap between the bit line structures; patterning the first dielectric layer and the first sacrificial layer to form a through hole, wherein the through hole and the remaining first dielectric layer and first sacrificial layer are alternately arranged; forming a second sacrificial layer on the side wall of the through hole, and filling the through hole to form a contact plug; forming a contact structure on the contact plug; and removing the first sacrificial layer to form a first air gap, and removing the second sacrificial layer to form a second air gap.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor technologies. The manufacturing method includes: providing a substrate and forming a film layer stack structure thereon; etching the film layer stack structure to form a first region containing a through hole through which the substrate is exposed and a second region containing a hole section through which the substrate is not exposed; and patterning and etching the second region to remove the film layer stack structure within the second region.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.

Abstract: A method for preparing a capacitor contact structure of a memory device includes providing a substrate, forming a plurality of bit line structures arranged in parallel and at intervals on the substrate, and the bit line structures extending along a first direction; forming conducting layer structures between adjacent bit line structures, upper surfaces of which are lower than upper surfaces of the bit line structures; forming sacrificial layers on the conducting layer structures; forming a plurality of isolation trenches arranged in parallel and at intervals in the sacrificial layer, the isolation trenches extend along a second direction, and the second direction intersects the first direction; forming isolation dielectric layers in the isolation trenches; and removing the sacrificial layer based on the bit line structure and the isolation dielectric layer to form grooves between adjacent bit line structures and between adjacent isolation dielectric layers, the grooves expose the conducting layer structures.

Abstract: A semiconductor structure and a chip are provided. The semiconductor structure includes: a first active area and a second active area extending along a first direction and having a first width in a second direction; a first WordLine (WL) drive transistor group including two gate dielectric areas connected to the first active area; a second WL drive transistor group including two gate dielectric areas connected to the first active area; a third WL drive transistor group including two gate dielectric areas connected to the second active area; and a fourth WL drive transistor group including two gate dielectric areas connected to the second active area. Each of the gate dielectric area extends along the second direction and has a second width in the first direction.

Abstract: An embodiment of the application provides a method for forming a semiconductor structure. The semiconductor structure includes a first region and a second region. The method includes the following steps: providing a base, an insulating layer, and a mask layer that are stacked in sequence, where the first region has at least one trench penetrating the mask layer and the insulating layer, and the mask layer has an upper surface in the second region higher than that in the first region; forming a first protection layer, where an upper surface and a sidewall of the mask layer in the first region are covered with the first protection layer; after the first protection layer is formed, removing the mask layer in the second region; subsequent to removal of the mask layer in the second region, removing the first protection layer; and removing the mask layer in the first region.

Abstract: A power supply circuit includes: power supplying module configured to provide DC voltage; transformer module including primary-side first winding connected to power supplying module and secondary-side winding coupled to primary-side first winding; switch module having one end connected to primary-side first winding and the other end connected to grounding terminal; control module connected to switch module, where control module is configured to control switch module to have different switching frequencies and/or different turning-off times, to enable first pulse voltages with different duty cycles to be formed on primary-side first winding, and second pulse voltages with different duty cycles to be subsequently generated on secondary-side winding; and voltage conversion module having input terminal connected to secondary-side winding and output terminal connected to voltage output terminal of power supply circuit, where voltage conversion module is configured to convert second pulse voltages with different du