Abstract: The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device. The method for manufacturing a semiconductor device includes: providing a substrate; forming a plurality of first structures extending in a first direction on the substrate; forming a sacrificial layer on sidewalls of the first structures; forming an outer spacer layer on a sidewall of the sacrificial layer; removing part of the outer spacer layer to obtain a patterned outer spacer layer that exposes part of the sacrificial layer; and removing the sacrificial layer to form air gaps between the patterned outer spacer layer and the first structures.

Abstract: A method for forming a capacitor via includes: providing a to-be-processed wafer, the to-be-processed wafer including a substrate and a first dielectric layer and a first mask layer that are sequentially formed on a surface of the substrate; etching the first mask layer according to a compensated first etching parameter, to form a first patterned layer extending in a first etching direction; sequentially forming a second dielectric layer and a second mask layer on a surface of the first patterned layer; etching the second mask layer and the second dielectric layer according to a compensated second etching parameter, to form a second patterned layer extending in a second etching direction; and etching the first dielectric layer with the first patterned layer and the second patterned layer together as a capacitor pattern, to form a capacitor via.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, wherein the base includes an active region and a shallow trench isolation structure separating the active region, a word line trench is formed in the base, and the word line trench exposes a part of the active region and the shallow trench isolation structure; forming a first intermediate structure in the word line trenches, wherein the first intermediate structure covers side walls and a bottom wall of the word line trench, a first trench is formed in the first intermediate structure, the first intermediate structure includes a sacrificial structure, and the sacrificial structure includes a horizontal portion; and removing the horizontal portion of the sacrificial structure, and closing the first trench, and forming an air chamber.

Abstract: Provided is a manufacturing method of a semiconductor structure, including: providing a substrate; forming a first mask layer having a first mask pattern on the substrate, and etching the substrate by using the first mask layer as a mask to form active regions; forming several discrete bitlines on the active regions; forming a sacrificial layer between adjacent bitlines; forming a second mask layer having a second mask pattern on the sacrificial layer, the first mask pattern and the second mask pattern being complementary to each other; and etching the sacrificial layer by using the second mask layer and the bitlines as masks to form a plurality of contact structures. The embodiment of the present disclosure is beneficial to reducing the manufacturing cost of the semiconductor structure.

Abstract: A semiconductor structure includes a substrate, an isolation structure formed in the substrate, and a word line including a first convex portion and a second convex portion. The first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.

Abstract: Embodiments provide an input buffer circuit and a semiconductor memory, a compensation subcircuit is provided between an input terminal of the input buffer circuit and a first terminal of a load subcircuit, a current of an output terminal of the input buffer circuit is increased, and voltage variation of the input terminal can be transmitted to the output terminal in time, such that the output terminal can timely receive the voltage variation of the input terminal, thereby avoiding distortion of an output signal, solving a problem of signal attenuation for the input buffer circuit, improving sensitivity of the input buffer circuit, and preventing negative effects from being caused to transmission of commands inside a system.

Abstract: A method for manufacturing the semiconductor structure includes: a substrate is provided; isolation structures having a first depth are formed in the substrate; word line structures having a second depth are formed in the substrate, where part of the word line structures are formed in respective ones of the isolation structures, and the second depth is less than the first depth; the isolation structures are etched in a direction perpendicular to the substrate to form a first trench having a third depth in each isolation structure; and a first insulating layer covering the word line structures and the first trenches is formed on the substrate to form an air gap structure in each isolation structure.

Abstract: Some embodiments of the present application disclose a polishing liquid supply system. In the present application, the polishing liquid supply system includes: a polishing liquid preparation device, a cleaning liquid supply device and a filtering device, and further includes a supply pipeline connected with the polishing liquid preparation device and the filtering device and a cleaning pipeline connected with the cleaning liquid supply device and the filtering device. The polishing liquid preparation device is configured to prepare a polishing liquid and convey the prepared polishing liquid to the filtering device through the supply pipeline. The filtering device is configured to filter the polishing liquid and convey the filtered polishing liquid to a polishing device connected with the filtering device. The cleaning liquid supply device is configured to convey a cleaning liquid to the filtering device through the cleaning pipeline.

Abstract: The present disclosure provides a method and an apparatus for detecting a data path, and a storage medium, relates to the technical field of semiconductors, and is applied to a process of detecting a data path of a semiconductor integrated circuit. The method for detecting a data path includes: disconnecting, by a detection apparatus, a connection between a global data line and a local data line in the data path, writing test data into the global data line in the data path via the data path through a write port of the data path, reading, by the detection apparatus, target data of the global data line under a preset condition, and further detecting a defect of the data path according to the test data and the target data.

Abstract: A method for forming a micro bump includes the following operations. A chip at least including a silicon substrate and a Through Silicon Via (TSV) penetrating through the silicon substrate is provided. A conductive layer having a first preset size in a first direction is formed in the TSV, the first direction being a thickness direction of the silicon substrate. A connecting layer having a second preset size in the first direction is formed on a surface of the conductive layer in the TSV, where a sum of the first preset size and the second preset size is equal to an initial size of the TSV in the first direction. The silicon substrate is processed to expose the connecting layer, for forming a micro bump corresponding to the TSV.

Abstract: A method for predicting an inclination angle of an etched hole can include operations as follows. A preset change range of an etching rate of an etching device for an object to be etched on a surface of a monitored sample in different operation stages is determined. An etching rate change curve of the etching device for the object to be etched on the surface of a monitored sample in a current operation stage is acquired. When the etching rate change curve exceeds the preset change range, it is determined that an inclination angle of an etched hole of an etched product currently etched by the etching device exceeds a preset angle.

Abstract: A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate, wherein the substrate includes a word line region, a bit line region, and a capacitive region arranged adjacently; forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure includes a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer; forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and performing an ion implantation on the first semiconductor layer and the second semiconductor layer.

Abstract: A method for temperature control includes: acquiring the present temperature of a reaction window in a process chamber of a semiconductor machine; comparing the present temperature with the preset temperature to acquire a comparison result; and adjusting the exhaust amount of an exhaust passage of the process chamber based on the comparison result to control the temperature of the reaction window.

Abstract: A fault isolation analysis method includes: providing a package structure in which there is an electrical fault; detecting whether the electrical fault is in interconnecting wires, and if the electrical fault is in the interconnecting wires, determining that the electrical fault is caused by the interconnecting wire; and if the electrical fault is not in the interconnecting wires, breaking the interconnecting wires to electrically isolate the chip structure from the substrate, then detecting whether the electrical fault is in the structure, and if the electrical fault is able to be detected, determining that the electrical fault is caused by the substrate, or if the electrical fault is not able to be detected, determining that the electrical fault is caused by the chip structure.

Abstract: A semiconductor memory includes a main memory area and a tag memory area. A plurality of memory groups are set in the main memory area and a plurality of flag bits are set in the tag memory area. Each of the plurality of memory groups has a corresponding relationship with one of the plurality of flag bit. The flag bit is at least configured to indicate whether at least one memory cell in the memory group has a specific state. The specific state includes an occupied state.

Abstract: An installation fixture for needle is used to install needles of an electrostatic chuck, and includes: a positioning tray, detachably disposed on an outer base of the electrostatic chuck, the positioning tray being provided with installation holes, and the installation holes corresponding to installation positions of the needles of the electrostatic chuck; and an installation fixture, detachably installed in the installation hole to adjust the installation depth of the needle.

Abstract: The data receiving circuit includes: a first amplification module configured to: receive a data signal, a first reference signal, and a second reference signal; and when an enable signal is at a first level, in response to a sampling clock signal and on a basis of a feedback signal, select the data signal and the first reference signal for first comparison and output a first signal pair, or select the data signal and the second reference signal for second comparison and output a second signal pair; and a second amplification module configured to receive output signals of the first amplification module as an input signal pair, perform amplification processing on a voltage difference of the input signal pair.

Abstract: The present disclosure provides an apparatus and a method for transferring a wafer, and an apparatus for controlling transferring a wafer. The apparatus for transferring a wafer includes a transfer chamber, at least one process chamber, a first detection unit, and a control unit, wherein the transfer chamber is provided therein with a transfer unit; the at least one process chamber is in connect with the transfer chamber, and a chamber door is provided at a connect position; the first detection unit includes a first transmit end and a first receive end, the first transmit end is provided on one of the transfer unit and the chamber door, and the first transmit end is provided on the other one of the transfer unit and the chamber door.

Abstract: Provided is a Plasma Induced Damage (PID) test structure and a semiconductor test structure, including: a gate structure, including a gate layer; a covering dielectric layer, located on a surface of the gate layer; a metal layer structure, located on a surface of the covering dielectric layer, the metal layer structure including at least one metal layer; and an extraction electrode, electrically connected with the gate layer via a conductive structure.