Abstract: The disclosed driver and memory include: a phase driver that receives a first voltage signal, configured to output a second phase signal according to the first phase signal and the first voltage signal; a complementary phase driver includes: a first inverter for generating a complementary inverted phase signal based on a first complementary phase signal, the first phase signal and the first complementary phase signal are mutually inverted; a second inverter for receiving an output signal of the first inverter and a second voltage signal, the voltage value of the second voltage signal is smaller than that of the first voltage signal, and the second inverter is configured to be based on the first complementary inverted phase signal, and the second voltage signal outputs a second complementary phase signal. The driver of the embodiment provides the second phase signal and the second complementary phase signal.

Abstract: A data input verification method and a data input verification structure are provided in the present disclosure. The data input verification method includes: generating a randomly combined input character string; generating a test input signal inputted to a receiver of a memory based on the input character string and a simulated inter-symbol interference value, where the simulated inter-symbol interference value is an estimated value of inter-symbol interference transmitted from an output end of a memory controller to the receiver; inputting the test input signal into the receiver and obtaining an output signal of the receiver; determining whether a string represented by the output signal is equal to the input string and generating an eye diagram of the output signal.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base having first contact layers and a second contact layer; forming an initial electrical connection layer; forming a lower mask layer including a first and a second pattern regions, and on an upper surface of the base, orthographic projections of two first contact layers fall within an orthographic projection of one first pattern region, and an orthographic projection of one second contact layer falls within an orthographic projection of one second pattern region; patterning the first pattern region to form two first sub-pattern regions discrete from each other; and etching the initial electrical connection layer to form first electrical connection layers and a second electrical connection layer discrete from each other, in which the first electrical connection layers correspond to the first sub-pattern regions, and the second electrical connection layer corresponds to the second pattern region.

Abstract: The application relates to an electrode layer, a capacitor and methods for electrode layer and capacitor manufacture. The method for electrode layer manufacture comprises the following steps: forming a first electrode layer, the first electrode layer comprising a doped Titanium Nitride (TiN) layer; and forming a second electrode layer on the surface of the first electrode layer, the second electrode layer comprising a TiN layer or a work function layer.

Abstract: A manufacturing method of a semiconductor structure includes: providing a base; forming multiple bit line structures on the base, where the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures; forming a first conductive layer in the trench, where a void is formed in the first conductive layer; removing a part of the first conductive layer to form a first groove, where the bottom of the first groove exposes the void; forming an epitaxial layer on an inner wall of the first groove; and allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void.

Abstract: Embodiments provide a control circuit and a dynamic random access memory. A first connector of the memory chip connects to an input terminal of a functional circuit via a first switch circuit, and an output terminal of the functional circuit connects to a second connector via a second switch circuit, where the first switch circuit and the second switch circuit correspond to a first switch state. A second connector is connected to an input terminal of a functional circuit via a third switch circuit, and an output terminal of the functional circuit is connected to the first connector via a fourth switch circuit, where the third switch circuit and the fourth switch circuit correspond to a second switch state. The switch circuit can control the first switch state or second switch state to be an on state on a basis of a location parity signal of the memory chip.

Abstract: A memory includes a substrate. An isolation layer is disposed on the substrate. The plurality of active regions arranged in an array are disposed in the isolation layer. A plurality of word lines are formed in the plurality of active regions and the isolation layer. Each word line includes gates disposed in the active regions and word line structures disposed in the isolation layer. The each word line is constituted by successive connection of the plurality of gates and the plurality of word line structures arranged at intervals. The plurality of gates included in the each word line are disposed in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are disposed in two correspondingly adjacent rows of active regions.

Abstract: A semiconductor structure includes: a substrate; a through silicon via structure that is located in the substrate; a first heat dissipation layer that is around a side wall of the through silicon via structure, and a material of which is a metal semiconductor compound; and a second heat dissipation layer that is around the side wall of the through silicon via structure and located between the first heat dissipation layer and the through silicon via structure, and a heat conductivity of which is greater than a heat conductivity of the first heat dissipation layer.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip, where a first conductive connection wire of the first chip is connected to a first conductive contact pad, a second conductive connection wire of the second chip is connected to a second conductive contact pad, the first conductive contact pad includes a first conductor group and a first connection group, and the second conductive contact pad includes a second conductor group and a second connection group.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The method for manufacturing a semiconductor device includes: providing a semiconductor substrate, with a plurality of trench isolation structures and a plurality of functional regions between the trench isolation structures being formed; forming a buried bit line structure, the buried bit line structure being formed in the semiconductor substrate; and forming a word line structure and a plurality of active regions, the word line structures and the active regions being formed on a surface of the semiconductor substrate and located above the functional regions.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including a plurality of lower electrode pillars that are arranged at intervals; a dielectric layer, at least partially covering a sidewall of each of the lower electrode pillars; a first upper electrode, covering a surface of the dielectric layer; a first support layer, located above the plurality of lower electrode pillars, the dielectric layer, and the first upper electrode, wherein the first support layer at least exposes a peripheral region of a part of the first upper electrode.

Abstract: A method for manufacturing a buried gate includes: providing a substrate; forming a word line trench in the substrate; treating a surface of the word line trench to form concave structures on the surface of the word line trench; and, forming a conductive layer in the word line trench, convex structures matched with the concave structures being provided on a surface of the conductive layer.

Abstract: A semiconductor structure includes a semiconductor substrate, a first isolation dam, a plurality of switching transistors and a second isolation dam. The semiconductor substrate includes a trench, an isolation region formed by a region where the trench is located, a plurality of active regions defined by the isolation region, and an electrical isolation layer, the electrical isolation layer being located on one side, away from an opening of the trench, of the trench; the first isolation dam fills the trench; the switching transistor is at least partially embedded in the active region of the semiconductor substrate; and the second isolation dam is at least partially located between the first isolation dam and the electrical isolation layer.

Abstract: Embodiments relate to the field of semiconductor technology, and proposes a semiconductor device and a memory. The semiconductor device includes a pull-up circuit integration region, a pull-down circuit integration region and a compensation circuit integration region not overlapped with one another. The semiconductor device further includes an output circuit, and the output circuit includes: a pull-up circuit, a pull-down circuit, and a compensation circuit. The pull-up circuit is connected to a signal output line, and the pull-up circuit is positioned in the pull-up circuit integration region. The pull-down circuit is connected to the signal output line, and the pull-down circuit is positioned in the pull-down circuit integration region. The compensation circuit is configured to enhance a drive capability of an output signal from the signal output line, and the compensation circuit is positioned in the compensation circuit integration region.

Abstract: A system for monitoring a closed state of a cover of an exposure machine includes a servo motor, a photoelectric encoder, and a controller. A shaft of the servo motor is coaxially fixedly connected to a shaft of the cover. The photoelectric encoder is provided on the servo motor, and is configured to detect an angle of rotation of the shaft of the servo motor. The controller is connected to the servo motor and the photoelectric encoder, and is configured to control rotation of the shaft of the servo motor and determine whether the cover is in the closed state according to the angle.

Abstract: A method for correcting a robot is provided. The method includes: providing a correction device, wherein the correction device comprises a jig wafer; grabbing and/or transferring the jig wafer by using the robot to obtain collected data; determining, based on the collected data, whether the robot needs to be corrected; and in response to that the robot needs to be corrected, obtaining a compensation value according to the collected data, and correcting the robot based on the compensation value.

Abstract: A sense amplifier includes an amplifying circuit and a voltage equalizing circuit. The amplifying circuit includes: a first P-type transistor, having a first terminal connected to a third node, a second terminal connected to a first node, and a gate connected to a first bit line; a second P-type transistor, having a first terminal connected to the third node, a second terminal connected to a second node, and a gate connected to a second bit line; a first N-type transistor, having a first terminal connected to the first node, a second terminal connected to a fourth node, and a gate connected to the first bit line; a second N-type transistor, having a first terminal connected to the second node, a second terminal connected to the fourth node, a gate connected to the second bit line. The voltage equalizing circuit is connected between the first node and the second node.

Abstract: An impedance matching circuit includes a driver circuit, a calibration circuit, a digital logic circuit, a receiving circuit and a first resistor. An output of the driver circuit is connected to the receiving circuit, and an output of the calibration circuit is connected to the first resistor. The calibration circuit is configured to cooperate with the driver circuit to perform calibration according to the impedance values of the first resistor and the receiving circuit to determine a plurality of calibration parameters obtained at different output level values. The digital logic circuit is configured to receive the plurality of calibration parameters and determine a respective target calibration parameter of each of the at least one transistor slice in the driver circuit. The driver circuit is configured to receive the target calibration parameter, and perform impedance adjustment on the at least one transistor slice according to the target calibration parameter.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, and forming a dielectric layer and a mask layer, where the mask layer is arranged with a first opening; forming a first barrier layer on a sidewall of the first opening, where the first barrier layer surrounds and forms a second opening; forming a second barrier layer filling the second opening; removing the first barrier layer and the second barrier layer by a first etching process until the first barrier layer or the second barrier layer is completely removed; and removing the dielectric layer exposed by the first opening and part of the substrate exposed by the first opening to form a bit-line contact opening.

Abstract: A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.