Abstract: The present application provides a temperature calibration method for a semiconductor machine, including following steps: providing at least one temperature calibration sheet, the temperature calibration sheet comprising a transistor having a voltage-temperature characteristic curve corresponding to a set current; placing the temperature calibration sheet in a measurement region of the semiconductor machine; energizing the temperature calibration sheet at an energizing current being the same as the set current, and measuring a voltage of the transistor; and, obtaining a temperature of the transistor according to the voltage-temperature characteristic curve of the transistor by using the voltage as a known parameter, the temperature being a temperature of the measurement region of the semiconductor machine. The accuracy of temperature calibration is greatly improved, the performance of the semiconductor machine and the yield of the semiconductor manufacturing process are also improved.

Abstract: A tag coordinate determination method includes: generating a tag unit for placing a detection tag; setting the detection tag and the tag unit in an image of a photomask, and obtaining a tag position file of the image, the tag position file including position coordinates of the tag unit in the image; and acquiring position coordinates of a tag to be processed in the image according to the tag position file. The tag coordinate determination method can overcome to a certain extent the problem of manually capturing the coordinates being prone to errors, thereby improving accuracy of coordinate determination.

Abstract: A semiconductor structure comprises: a substrate; a first transistor including a first gate located in the substrate and a first terminal located on a surface of the substrate, the first terminal being configured to be connected to a first-type memory cell; and a second transistor including a second gate located in the substrate and a second terminal located on the surface of the substrate, the second terminal being configured to be connected to a second-type memory cell, and a width of the second gate being less than a width of the first gate.

Abstract: Embodiments of the disclosure provide a system and method for adjusting an oxygen content in an FOUP. The system for adjusting the oxygen content in the FOUP includes an inflating assembly, the FOUP, a controller and a detecting assembly; the inflating assembly is connected with a gas inlet of the FOUP and configured to input an inert gas to the FOUP; the detecting assembly is connected with a gas outlet of the FOUP and configured to detect the oxygen content of the gas in the FOUP; and the inflating assembly and the detecting assembly are both connected with the controller, and the controller is configured to adjust a flow of the inert gas input from the inflating assembly to the FOUP according to the oxygen content detected by the detecting assembly.

Abstract: Embodiments of the present disclosure provide a forming method of a semiconductor structure and a semiconductor structure. The forming method includes: providing a base, the base includes a central region and dummy regions, and the central region includes a molding region and cutting regions; forming multiple spaced core pillars on the base; forming an initial mask layer surrounding and covering a sidewall of each core pillar on the base; removing the initial mask layers located in each cutting region to form multiple spaced mask sidewall strips in the molding region, and retaining at least one of the initial mask layers in each dummy region as a ring-shaped sidewall; removing the core pillars located in the central region and the dummy regions; and etching the base to form multiple functional structures, and etching the base to form dummy functional structures on two sides of the multiple functional structures.

Abstract: A compensation method and system for exposure alignment are provided. The method includes: acquiring original data of an aligned pattern, performing first-order processing on the original data to obtain first-order derivative data, obtaining a compensation value based on the original data and the first-order derivative data when exposure alignment has deviation, and compensating the exposure alignment based on the compensation value. According to the compensation method for exposure alignment, the first-order derivative data is obtained by performing first-order processing on the original data, and then the compensation value is obtained based on the original data and the first-order derivative data to compensate the exposure alignment, so that the compensation accuracy is higher, and the accuracy of exposure alignment is optimized.

Abstract: A memory chip test method includes: a mode register write command is sent to a memory chip to control a memory chip to enter a test mode of Write Clock to clock leveling (Wck2ck Leveling); a first preset time is set, and a read and write clock signal is sent to the memory chip after waiting for the first preset time; a predicted value of the Wck2ck Leveling is determined according to the first preset time and a system clock cycle; after sending the read and write clock signal and waiting for a second preset time, a test data output port of the memory chip is detected to obtain a test value; and the test value and the predicted value are compared to determine whether the memory chip is abnormal. A method for testing a Wck2ck Leveling function is provided.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate, and forming a first sacrificial layer on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer; patterning the first sacrificial layer, and forming first intermediate pattern structures that are arranged at intervals, where a first gap is provided between two adjacent first intermediate pattern structures; forming a first spacer pad layer in the first gap, where the first spacer pad layer covers sidewalls of each of the two adjacent first intermediate pattern structures and a bottom of the first gap; removing the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer; and removing the first sacrificial dielectric layer, to form first pattern structures.

Abstract: A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.

Abstract: A storage system for reticles includes carrier devices, including reticle placing regions for placing the reticles; a storage device, storing a preset coordinate system and position information of the carrier devices in the preset coordinate system; detection devices, arranged in one-to-one correspondence with the carrier devices, where each detection device performs reticle detection on a respective carrier device, send first detection signal responsive to a reticle being placed in the reticle placing region, and send second detection signal responsive to a reticle being placed outside the reticle placing region, the detection devices are connected with the storage device, and the storage device is further configured to store reticle position information of the reticle in the preset coordinate system when receiving the first or second detection signal; and alarm devices, connected with the detection devices in one-to-one correspondence, where each alarm device implements alarm display when receiving the seco

Abstract: Embodiments provide a command processing circuit and a data processing circuit, including a plurality of flip-flops. An output terminal of a former flip-flop is connected to an input terminal of a latter flip-flop. The flip-flop is configured to sample, according to switching of a data strobe signal, an internal write command inputted into the command processing circuit to obtain a sampling command, to sample data. An output terminal of a target flip-flop is connected to a target terminal of a first flip-flop, the target flip-flop is a flip-flop whose time of outputting an active level overlaps target time, where the target time is start time and/or end time of a pulse in the internal write command. The target flip-flop is configured to reset the internal write command in the first flip-flop by outputting the active level.

Abstract: A method for forming a semiconductor structure and the semiconductor structure are provided. The method for forming the semiconductor structure includes: providing a substrate, wherein a separate bit line structure is formed on the substrate; forming a first sacrificial layer on the side wall of the bit line structure; forming a first dielectric layer filling gap between the bit line structures; patterning the first dielectric layer and the first sacrificial layer to form a through hole, wherein the through hole and the remaining first dielectric layer and first sacrificial layer are alternately arranged; forming a second sacrificial layer on the side wall of the through hole, and filling the through hole to form a contact plug; forming a contact structure on the contact plug; and removing the first sacrificial layer to form a first air gap, and removing the second sacrificial layer to form a second air gap.

Abstract: The present disclosure provides a memory array, a memory cell, and a data read and write method thereof. Two storage nodes are provided in each memory cell of a memory array of a magnetic random access memory (MRAM), such that when one storage node in the memory cell fails, the other storage node in the memory cell can be used to write and read data.

Abstract: An overhead buffer double-entry detection system, which includes an overhead hoist transport, a first sensing unit for scanning and generating detection data of a horizontal range, a driving device for moving the first sensing unit in a vertical range, a controlling unit, and an overhead hoist transport controlling system for sending a detection instruction and a driving instruction to the controlling unit when the overhead hoist transport moves to a corresponding overhead buffer position, whereby the controlling unit bases on the driving instruction to control the driving device to move the first sensing unit in a vertical range, bases on the detection instruction to control the first sensing unit to scan and generate detection data of each horizontal range within the overhead buffer during movement process, and bases on the detection data of each horizontal range within the overhead buffer to judge whether there is obstacle in the overhead buffer.

Abstract: An injection mould and an injection moulding method are provided. The injection mould includes: a base plate, configured to place a package chip to be injection-moulded, the package chip including a substrate and at least one chip fixed on a surface of the substrate by a flip chip process, the substrate having a through hole, a glue injection channel being formed in the base plate and configured to inject a moulding compound, and the glue injection channel being connected with the through hole on the substrate. The above-mentioned injection mould can improve the reliability of the package chip after injection moulding.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes a semiconductor base, a bit line and a word line. The semiconductor base includes a substrate and an isolation structure. The isolation structure is arranged above the substrate and configured to isolate a plurality of active regions from each other. The bit line is arranged in the substrate and connected to the plurality of active regions. The word line is arranged in the isolation structure, intersects with the plurality of active regions and surrounds the plurality of active regions. The substrate is a Silicon-On-Insulator (SOI) substrate.

Abstract: A sense amplifier circuit, memory device and related operation methods are provided. The sense amplifier circuit includes an amplification circuit for amplifying a voltage signal and a compensation circuit coupled to the amplification circuit. The amplification circuit includes a first inverting amplifier and a second inverting amplifier cross-coupled with each other, with the first inverting amplifier connected to a first bitline and the second inverting amplifier connected to a second bitline. The compensation circuit includes a first, a second, a third, and a fourth switch circuits, and is configured to generate a compensation voltage between the first bitline and the second bitline by conducting charge injections through operating the switch circuits to compensate an input-referred offset voltage of the amplification circuit.

Abstract: The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory. The method for manufacturing a semiconductor structure includes the following steps: providing a substrate, and forming a stabilizing layer on the substrate; forming a stabilizing structure consisting of a plurality of linear structures and grooves among the linear structures; forming a hard mask layer covering the stabilizing structure; forming a mask pattern connected to a top of the linear structure and an inner wall of the groove on the hard mask layer; and transferring the mask pattern to the substrate.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method includes: providing a substrate including a core NMOS area, a core PMOS area and a peripheral NMOS area; performing oxidation treatment on the substrate in the core PMOS area to convert a thickness of a part of the substrate in the core PMOS area into an oxide layer; removing the oxide layer; forming a first semiconductor layer on the remaining substrate in the core PMOS area; forming a gate dielectric layer located on the first semiconductor layer and on the substrate in the core NMOS area and the peripheral NMOS area; and forming a gate on the gate dielectric layer.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes following operations. A substrate including active regions and isolation regions is provided. First trench structures are formed on the substrate, the first trench structure passing through the active region and the isolation region. Bit line contact structures are formed in the first trench structures. Bit line structures are formed on the bit line contact structures, at least part of the bit line structure being positioned in the first trench structure. Bit line protection structures are formed on the bit line structures, the bit line protection structure at least covering an upper surface of the bit line structure. Capacitor contact assemblies are formed, the capacitor contact assembly including a first capacitor contact structure and a second capacitor contact structure which covers an upper surface and part of a side wall of the first capacitor contact structure.