Abstract: A voltage detection circuit including a threshold setting module and a voltage conversion module, and a voltage detection method are provided. In the threshold setting module, a first input end is configured to receive a voltage to be detected, a second input end is configured to receive a threshold regulation signal, a power supply end is connected to a first voltage and is configured to set a voltage regulation range according to the threshold regulation signal, determine a first voltage regulation value in the voltage regulation range according to the voltage to be detected, and generate a control voltage according to the first voltage and the first voltage regulation value. The voltage conversion module is configured to output a first level when the control voltage is greater than a preset value and output a second level when the control voltage is less than or equal to the preset value.

Abstract: The present disclosure provides a chemical solution preparation system and method. The chemical solution preparation system includes: a first mixing system, configured to mix a first chemical solution and a first diluent to obtain a first mixture; a second mixing system, configured to mix a second chemical solution and a second diluent to obtain a second mixture; a third mixing system, configured to mix the first mixture, the second mixture, and a third diluent to obtain a third mixture; an output system, configured to output the third mixture to a spray apparatus of the chemical mechanical polishing device; a sampling system, configured to collect a sample of the third mixture output from the output system; and a monitoring system, configured to monitor a status of the first mixture, a status of the second mixture, and a status of the third mixture.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof, including: providing a substrate and a plurality of discrete bit line structures, the bit line structures being located on the substrate, capacitor contact windows being provided between adjacent bit line structures; forming first isolation layers, the first isolation layers covering sidewalls of the bit line structures; forming a sacrificial layer, the sacrificial layer covering sidewalls of the first isolation layers; forming second isolation layers, the second isolation layers covering sidewalls of the sacrificial layer and exposing the top surfaces and bottoms of the sacrificial layer; etching the exposed bottoms of the sacrificial layer to form bottom gaps between the first isolation layers and the second isolation layers; etching the exposed top surfaces of the sacrificial layer to remove the remaining of the sacrificial layer so as to form gaps between the layers.

Abstract: Embodiments relate to a decoder driver circuit and a memory chip. The decoder driver circuit includes: a plurality of sub drive units configured to generate a main word line drive signal according to a power supply voltage signal, a first decoding input signal and an intermediate decoding output signal; and a plurality of decoding control circuits connected to the plurality of sub drive units, where the plurality of decoding control circuits are configured to generate the intermediate decoding output signal according to an enable control signal and a second decoding input signal. When the intermediate decoding output signal is in a first state, the main word line drive signal is in a non-drive state.

Abstract: Provided are a memory cell structure, a memory array structure, a semiconductor structure and a manufacturing method thereof. The memory cell structure includes: a substrate, an active region, a word line structure, an insulating dielectric layer, and a capacitor structure. The substrate has a bit line structure therein, and the active region is positioned on the bit line structure. In a direction perpendicular to the substrate, the active region includes a first connection terminal, a second connection terminal away from the first connection terminal, and a channel region positioned between the first connection terminal and the second connection terminal. In the direction perpendicular to the substrate, the word line structure covers a sidewall of the channel region. The insulating dielectric layer covers an outer side of the word line structure, an outer side of the first connection terminal, and an outer side of the second connection terminal.

Abstract: The present disclosure provides a data receiving circuit, a data receiving system, and a memory device. The data receiving circuit includes: a receiving module, configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a sampling clock signal, and output a first output signal and a second output signal; and a decision feedback equalization module, connected to a feedback node of the receiving module, and configured to perform a decision feedback equalization on the receiving module on the basis of a feedback signal to adjust the first output signal and the second output signal, wherein the feedback signal is obtained on the basis of data received previously, and an adjustment capability of the decision feedback equalization module to the first output signal and the second output signal is adjustable.

Abstract: A semiconductor device includes a semiconductor substrate, a word line trench and a word line structure. The word line trench includes a first word line trench and a second word line trench. The word line structure includes a first word line structure part and a second word line structure part connected to each other. The first word line structure part is formed in the first word line trench, and the second word line structure part is formed in the second word line trench; and the first word line structure part includes an avoidance region, and the top surface of the avoidance region is aligned with the top surface of the second word line structure part, and the avoidance region is provided with insulating material.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, and a first bonding structure and a first conductive via which are formed in the first substrate. The first bonding structure includes a first metal layer and a second metal layer with a melting point lower than a melting point of the first metal layer. The first metal layer includes a first surface and a second surface arranged opposite to each other. The first surface of the first metal layer is provided with a first groove, and the second metal layer is arranged in the first groove. The first conductive via is in contact with the second surface of the first metal layer. A projection of the first conductive via coincides with a projection of the first groove in a direction perpendicular to the first surface of the first metal layer.

Abstract: A photomask protection device, a photomask protection system, and a use method of a photomask protection system are provided. The photomask protection device includes a frame and a pellicle. The frame is disposed on a substrate of a photomask and is provided with a clamping space. Edges of the pellicle are fixed in the clamping space.

Abstract: Embodiments provide method for fabricating a semiconductor structure, and a semiconductor structure. The method includes: providing a substrate, a thin-film stack structure being formed on the substrate; forming a first groove and a second groove in the thin-film stack structure, and forming write transistors in the first groove, the second groove extending along a first direction, and the second groove being positioned between adjacent two of the write transistors in a second direction; removing a part of the thin-film stack structure by etching using the second groove to form a first hole and a second hole respectively, forming a write word line in the first hole, and forming a write bit line in the second hole; forming a first via on an upper surface of the thin-film stack structure, and forming a storage node in the first via; and forming a read transistor, a read bit line and a lead.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

Abstract: An in-memory computing circuit includes an initial computing circuit and a target computing circuit. Herein, the initial computing circuit is configured to perform first operation processing on first data and second data to output a first operation result, and perform second operation processing on the first data and the second data to output a second operation result. The target computing circuit is configured to perform the first operation processing on the second operation result and the first operation result to output a first target result, and perform the second operation processing on the first data and the second operation result to output a second target result.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, and a semiconductor structure. The manufacturing method of a semiconductor structure includes: forming a plurality of cylindrical capacitors in an initial structure; removing part of the initial structure to form trenches, the trenches expose partial sidewalls of the cylindrical capacitors and a substrate of the initial structure; forming a dielectric layer, the dielectric layer at least covers an exposed surface of each of the cylindrical capacitors; forming a first top electrode, the first top electrode covers a surface of the dielectric layer; and forming a second top electrode, the second top electrode covers a surface of the first top electrode. In an axial direction of each of the cylindrical capacitors, the second top electrode formed in each of the trenches has a discontinuous part, and an air gap is formed in the discontinuous part of the second top electrode.

Abstract: Provided are a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory. The method includes the following operations. An initial semiconductor structure is formed on a substrate. The initial semiconductor structure is etched to form an array area structure and a peripheral area structure including a peripheral area gate structure. An isolation wall surrounding the peripheral area gate structure is formed on the substrate where the peripheral area structure locates. A second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure. The second dielectric layer, the first dielectric layer and the isolation wall are etched to form the semiconductor structure with a flat surface.

Abstract: A semiconductor structure includes a plurality of metal layers and a substrate. The plurality of metal layers are provided with a plurality of virtual metal blocks and at least one signal line. A first projection of a first virtual metal block on the substrate is a polygon, the first projection has a plurality of effective sides opposite to a second projection of a target signal line on the substrate, and differences from the plurality of effective sides of the first projection to a straight line where the second projection is located are different, and the first virtual metal block is a virtual metal block, closest to the target signal line, on the target metal layer, and the target metal layer is a metal layer where the target signal line is located.

Abstract: The embodiments of the present disclosure provide a polishing head management system and method. The polishing head management system includes: a storage device, a pick-and-place device and a data acquisition device, where the storage device is used to store polishing heads; the pick-and-place device is used to pick a polishing head or place a polishing head into the storage device; the data acquisition device is connected with the storage device and the pick-and-place device, and is used to record at least one management cycle of the polishing head.

Abstract: A sense amplifier circuit architecture includes a first NMOS layout, a second NMOS layout, a first PMOS layout, a second PMOS layout, a first processing structure layout and a second processing structure layout. The first NMOS layout includes first N-type active layers and first gate layers discretely arranged on the first N-type active layers. The second NMOS layout includes second N-type active layers and second gate layers discretely arranged on the second N-type active layers. The first PMOS layout includes first P-type active layers and third gate layers discretely arranged on the first P-type active layers. The second PMOS layout includes second P-type active layers and fourth gate layers discretely arranged on the second P-type active layers. The first processing structure layout includes first active layers and a first isolation gate. The second processing structure layout includes second active layers and a second isolation gate.

Abstract: A manufacturing method of a semiconductor structure includes the following operations. A substrate is provided, which includes a first N region, a first P region, a second N region and a second P region adjacently arranged in sequence. A gate dielectric layer, a first barrier layer, a first work function layer and a second barrier layer are formed on the substrate in sequence. A mask layer is formed on the second barrier layer of the first P region and the second P region. The second barrier layer of the first N region and the second N region is removed by a first etching process with the mask layer as a mask. The first work function layer and the first barrier layer of the first N region and the second N region are removed by a second etching process. A semiconductor structure is also provided.

Abstract: A semiconductor structure includes a substrate, a via, a conductive pillar, and a core layer. The via is located in the substrate. The conductive pillar is located in the via, and the conductive pillar is provided with a groove extended inwards from an upper surface of the conductive pillar. The core layer is located in the groove, a Young modulus of the core layer is less than that of the conductive pillar.

Abstract: A signal detection system and a memory detection method are provided. The system includes a signal generator, generating a reference test signal based on an external parameter, the reference test signal being a clock signal satisfying a preset duty cycle, where a duty cycle test is performed on the reference test signal based on a test circuit, to determine whether a function of the test circuit is normal. If the function of the test circuit is normal, different portions under test are sequentially selected based on a test control signal, and the duty cycle test is performed, based on the test circuit, on a signal outputted by each of the selected portions under test. The portions under test include a signal converter and a write clock path.