Abstract: The present disclosure relates to the technical field of semiconductors, and provides an electro-static discharge (ESD) protection structure and a chip. The ESD protection structure includes: a semiconductor substrate, a first P-type well, a first N-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, a second P-type doped portion, a third doped well, a third P-type doped portion and a third N-type doped portion, wherein the first P-type well, the first N-type well and the third doped well are located in the semiconductor substrate; the first N-type doped portion and the first P-type doped portion are located in the first N-type well and spaced apart; the second N-type doped portion and the second P-type doped portion are located in the first P-type well and spaced apart.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: depositing a thin-film stacked structure on a substrate; forming a first hole in the thin-film stacked structure; growing an epitaxial silicon pillar in the first hole; etching the thin-film stacked structure and the epitaxial silicon pillar along a first direction to form a first trench, the first trench passing through a center of the epitaxial silicon pillar and dividing the epitaxial silicon pillar into a first half pillar and a second half pillar; forming a first isolation layer; forming a first channel region of a first doping type, and forming a second channel region of a second doping type; and forming a gate dielectric layer and a gate conductive layer on a surface of each of the first channel region and the second channel region.

Abstract: A bias generation circuit and a memory circuit are provided. The bias generation circuit includes: a first load circuit coupled between a working voltage and an regulating node; a bias circuit configured to receive the working voltage and output a bias voltage according to the working voltage; a voltage stabilizing circuit coupled to an output end of the bias circuit and configured to receive a reference voltage and regulate a voltage of the regulating node according to the bias voltage and the reference voltage; and a second load circuit having one end coupled to the output end of the bias circuit and the other end coupled to the regulating node.

Abstract: A comparator circuit includes a first transistor, a second transistor, a load circuit, a first adjustment circuit and a second adjustment circuit. A terminal of the first transistor is coupled to a first node, another terminal of the first transistor is coupled to a first control node, and a gate of the first transistor is configured to receive a first control signal. A terminal of the second transistor is coupled to the first node, another terminal of the second transistor is coupled to a second control node, and a gate of the second transistor is configured to receive a second control signal. A terminal of the load circuit is coupled to a second node, and another terminal of the load circuit is coupled to the first control node and the second control node.

Abstract: A data input verification method and a data input verification structure are provided in the present disclosure. The data input verification method includes: generating a randomly combined input character string; generating a test input signal inputted to a receiver of a memory based on the input character string and a simulated inter-symbol interference value, where the simulated inter-symbol interference value is an estimated value of inter-symbol interference transmitted from an output end of a memory controller to the receiver; inputting the test input signal into the receiver and obtaining an output signal of the receiver; determining whether a string represented by the output signal is equal to the input string and generating an eye diagram of the output signal.

Abstract: A semiconductor structure includes: a substrate; a through silicon via structure that is located in the substrate; a first heat dissipation layer that is around a side wall of the through silicon via structure, and a material of which is a metal semiconductor compound; and a second heat dissipation layer that is around the side wall of the through silicon via structure and located between the first heat dissipation layer and the through silicon via structure, and a heat conductivity of which is greater than a heat conductivity of the first heat dissipation layer.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, including a plurality of lower electrode pillars that are arranged at intervals; a dielectric layer, at least partially covering a sidewall of each of the lower electrode pillars; a first upper electrode, covering a surface of the dielectric layer; a first support layer, located above the plurality of lower electrode pillars, the dielectric layer, and the first upper electrode, wherein the first support layer at least exposes a peripheral region of a part of the first upper electrode.

Abstract: A manufacturing method of a semiconductor structure includes: providing a base; forming multiple bit line structures on the base, where the multiple bit line structures are parallel to each other and extend in a first direction, and a trench is formed between adjacent bit line structures; forming a first conductive layer in the trench, where a void is formed in the first conductive layer; removing a part of the first conductive layer to form a first groove, where the bottom of the first groove exposes the void; forming an epitaxial layer on an inner wall of the first groove; and allowing the epitaxial layer to epitaxially grow to form an extension portion, such that the extension portion fills the void.

Abstract: Embodiments relate to the field of semiconductor technology, and proposes a semiconductor device and a memory. The semiconductor device includes a pull-up circuit integration region, a pull-down circuit integration region and a compensation circuit integration region not overlapped with one another. The semiconductor device further includes an output circuit, and the output circuit includes: a pull-up circuit, a pull-down circuit, and a compensation circuit. The pull-up circuit is connected to a signal output line, and the pull-up circuit is positioned in the pull-up circuit integration region. The pull-down circuit is connected to the signal output line, and the pull-down circuit is positioned in the pull-down circuit integration region. The compensation circuit is configured to enhance a drive capability of an output signal from the signal output line, and the compensation circuit is positioned in the compensation circuit integration region.

Abstract: A memory includes a substrate. An isolation layer is disposed on the substrate. The plurality of active regions arranged in an array are disposed in the isolation layer. A plurality of word lines are formed in the plurality of active regions and the isolation layer. Each word line includes gates disposed in the active regions and word line structures disposed in the isolation layer. The each word line is constituted by successive connection of the plurality of gates and the plurality of word line structures arranged at intervals. The plurality of gates included in the each word line are disposed in two correspondingly adjacent columns of active regions, and any two adjacent gates in the each word line are disposed in two correspondingly adjacent rows of active regions.

Abstract: A method for manufacturing a buried gate includes: providing a substrate; forming a word line trench in the substrate; treating a surface of the word line trench to form concave structures on the surface of the word line trench; and, forming a conductive layer in the word line trench, convex structures matched with the concave structures being provided on a surface of the conductive layer.

Abstract: The present disclosure provides a semiconductor device and a manufacturing method thereof. The method for manufacturing a semiconductor device includes: providing a semiconductor substrate, with a plurality of trench isolation structures and a plurality of functional regions between the trench isolation structures being formed; forming a buried bit line structure, the buried bit line structure being formed in the semiconductor substrate; and forming a word line structure and a plurality of active regions, the word line structures and the active regions being formed on a surface of the semiconductor substrate and located above the functional regions.

Abstract: Embodiments provide a control circuit and a dynamic random access memory. A first connector of the memory chip connects to an input terminal of a functional circuit via a first switch circuit, and an output terminal of the functional circuit connects to a second connector via a second switch circuit, where the first switch circuit and the second switch circuit correspond to a first switch state. A second connector is connected to an input terminal of a functional circuit via a third switch circuit, and an output terminal of the functional circuit is connected to the first connector via a fourth switch circuit, where the third switch circuit and the fourth switch circuit correspond to a second switch state. The switch circuit can control the first switch state or second switch state to be an on state on a basis of a location parity signal of the memory chip.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base having first contact layers and a second contact layer; forming an initial electrical connection layer; forming a lower mask layer including a first and a second pattern regions, and on an upper surface of the base, orthographic projections of two first contact layers fall within an orthographic projection of one first pattern region, and an orthographic projection of one second contact layer falls within an orthographic projection of one second pattern region; patterning the first pattern region to form two first sub-pattern regions discrete from each other; and etching the initial electrical connection layer to form first electrical connection layers and a second electrical connection layer discrete from each other, in which the first electrical connection layers correspond to the first sub-pattern regions, and the second electrical connection layer corresponds to the second pattern region.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first chip and a second chip, where a first conductive connection wire of the first chip is connected to a first conductive contact pad, a second conductive connection wire of the second chip is connected to a second conductive contact pad, the first conductive contact pad includes a first conductor group and a first connection group, and the second conductive contact pad includes a second conductor group and a second connection group.

Abstract: A semiconductor structure includes a semiconductor substrate, a first isolation dam, a plurality of switching transistors and a second isolation dam. The semiconductor substrate includes a trench, an isolation region formed by a region where the trench is located, a plurality of active regions defined by the isolation region, and an electrical isolation layer, the electrical isolation layer being located on one side, away from an opening of the trench, of the trench; the first isolation dam fills the trench; the switching transistor is at least partially embedded in the active region of the semiconductor substrate; and the second isolation dam is at least partially located between the first isolation dam and the electrical isolation layer.

Abstract: The application relates to an electrode layer, a capacitor and methods for electrode layer and capacitor manufacture. The method for electrode layer manufacture comprises the following steps: forming a first electrode layer, the first electrode layer comprising a doped Titanium Nitride (TiN) layer; and forming a second electrode layer on the surface of the first electrode layer, the second electrode layer comprising a TiN layer or a work function layer.

Abstract: A tag coordinate determination method includes: generating a tag unit for placing a detection tag; setting the detection tag and the tag unit in an image of a photomask, and obtaining a tag position file of the image, the tag position file including position coordinates of the tag unit in the image; and acquiring position coordinates of a tag to be processed in the image according to the tag position file. The tag coordinate determination method can overcome to a certain extent the problem of manually capturing the coordinates being prone to errors, thereby improving accuracy of coordinate determination.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, and forming a dielectric layer and a mask layer, where the mask layer is arranged with a first opening; forming a first barrier layer on a sidewall of the first opening, where the first barrier layer surrounds and forms a second opening; forming a second barrier layer filling the second opening; removing the first barrier layer and the second barrier layer by a first etching process until the first barrier layer or the second barrier layer is completely removed; and removing the dielectric layer exposed by the first opening and part of the substrate exposed by the first opening to form a bit-line contact opening.

Abstract: A semiconductor structure comprises: a substrate; a first transistor including a first gate located in the substrate and a first terminal located on a surface of the substrate, the first terminal being configured to be connected to a first-type memory cell; and a second transistor including a second gate located in the substrate and a second terminal located on the surface of the substrate, the second terminal being configured to be connected to a second-type memory cell, and a width of the second gate being less than a width of the first gate.