Abstract: A conductive structure includes: a conductive pillar and at least one embedded block arranged in the conductive pillar, a coefficient of thermal expansion of the embedded block being less than that of the conductive pillar. When the conductive pillar is heated and expanded, an extrusion effect of the conductive pillar on a structure adjacent to the conductive pillar can be reduced, thereby improving the performance of the semiconductor structure.

Abstract: A test board for testing a memory signal includes a first surface and a second surface. The first surface of the test board comprises a raised region and a non-raised region. The raised region is provided with a first connection area connectable to a main board, and a level at which the raised is located is higher than a level at which the non raised region is located by a preset value. The second surface of the test board includes a test area and a second connection area connectable to a memory chip. The test board is provided with a first connection harness for connecting the test area to the first connection area and a second connection harness for connecting the test area to the second connection area, to enable the memory signal of the memory chip to be tested based on the test area.

Abstract: A testing method includes: a wafer under test is detected based on a pre-set test region to obtain detection results of a plurality of chips in the wafer under test; a discrete point distribution diagram of the detection results of the plurality of chips are obtained, a discrete point in the discrete point distribution diagram being used for representing a position of an abnormal chip in the wafer under test; the discrete point distribution diagram is divided into a plurality of test regions based on graphic distribution characteristics in the pre-set test region, and a test result distribution diagram for representing graphic characteristics of the discrete point distribution diagram is obtained; a correlation between the test result distribution diagram and the graphic distribution characteristics in the pre-set test region is obtained; and a test result of the wafer under test is obtained based on the correlation.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate; forming a first insulating layer covering the substrate, and patterning the first insulating layer to form a plurality of vias and a plurality of isolation structures that are alternatingly distributed; forming conductive contact plugs in the vias respectively, where the conductive contact plugs cover bottoms of the vias and each includes a first region and a second region adjacent to each other, and the conductive contact plugs located in the first regions cover outer walls of the isolation structures and extend along the outer walls to surfaces of the isolation structures distal from the substrate; and forming a passivation layer covering side walls and surfaces of the conductive contact plugs.

Abstract: The present disclosure provides a semiconductor memory device and a manufacturing method thereof. The manufacturing method includes: providing a substrate having a plurality of active areas; forming a plurality of bit line structures on the substrate, where the plurality of bit line structures are sequentially provided at intervals along a first direction; forming a dielectric layer on the substrate; etching the dielectric layer, to form a plurality of contact holes and a plurality of isolation structures, where each contact hole is between the adjacent bit line structures, the plurality of contact holes and the plurality of isolation structures are alternately provided along a second direction, the first direction is not parallel to the second direction; and forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure.

Abstract: A semiconductor structure includes: a substrate and a dielectric layer, in which the substrate has a front surface and a back surface which are oppositely arranged, and the dielectric layer is formed on the front surface; a connecting hole, penetrating through the substrate and extending to the dielectric layer; an insulating layer, located on the surface of the inner wall of the connecting hole; and a connecting structure, comprising a first barrier layer, a second barrier layer and a conductive structure, in which the first barrier layer is located on a surface of the insulating layer, the second barrier layer is located between the first barrier layer and the conductive structure, and an air gap exists between the second barrier layer and the first barrier layer.

Abstract: A method for correcting a mask patter includes: acquiring an initial pattern of a mask, the initial pattern including a scribe line area and die areas which are spaced, and the scribe line area is located between two adjacent die areas, each of the die areas includes at least one die sub-area and at least one first sub-test element group (TEG) area, and the scribe line area includes scribe line sub-areas and second sub-TEG areas, the first sub-TEG area and the second sub-TEG area are adjacent to each other, and the first sub-TEG area and the second sub-TEG area constitute a TEG area; performing an optical proximity correction (OPC) on an area of the initial pattern excluding TEG areas, so as to acquire a final pattern.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing a semiconductor structure includes: forming a plurality of capacitor holes on a substrate, and exposing a part of the substrate on bottoms of the capacitor holes; forming a bottom electrode layer on surfaces of the capacitor holes; forming, on a surface of the bottom electrode layer, a dielectric layer continuously covering the surface of the bottom electrode layer; forming a first top electrode layer to continuously cover a surface of the dielectric layer by a first film forming process; by a second film forming process, forming, in a circumferential direction of the capacitor holes, a second top electrode layer continuously covering a surface of the first top electrode layer, and forming, in an axial direction of the capacitor holes.

Abstract: A semiconductor structure includes a base, a conductive pillar at least located in the base, connecting structures and an electrical connection layer. At least one connecting structure is electrically connected to an end of the conductive pillar, the material of the connecting structure is different from that of the conductive pillar, and a total area of an orthographic projection of the connecting structure on the base is less than an area of an orthographic projection of the conductive pillar on the base. The electrical connection layer is electrically connected to an end of the connecting structure distal from the conductive pillar.

Abstract: A method for pushing a key includes the following steps: setting a plurality of keys, each of which corresponds to a different encrypted environment; configuring a user terminal with an environment switching interface for selection of an encrypted environment; and pushing a corresponding key to the user terminal according to a received key acquisition request.

Abstract: A semiconductor apparatus includes a substrate and a through silicon via (TSV) structure; a groove is disposed on the substrate; the TSV structure is disposed on the substrate; and a first end of the TSV structure is exposed in the groove, and a distance between an end surface of the first end and a bottom wall of the groove is smaller than the depth of the groove. The first end of the TSV structure is exposed so as to facilitate heat dissipation; the distance between the end surface of the first end and the bottom wall of the groove is smaller than the depth of the groove, i.e., the first end of the TSV structure is sunken in the groove, and other structures will not be affected.

Abstract: The present disclosure provides a data processing circuit and method, and a semiconductor memory, relating to the field of storage technologies. The circuit includes: a data selection module configured to receive and output write data if a received write control command is in a first level state, and receive and output read data if a received read control command is in the first level state; a check module configured to receive the write data or the read data, check the write data or the read data, and obtain write check data or read check data, and output the write check data or the read check data; and a data output module configured to receive the write check data or the read check data, output the write check data if the write control command is in the first level state.

Abstract: The present disclosure relates to a semiconductor mark and a forming method thereof. The semiconductor mark comprises: a previous layer mark comprising first patterns and at least one second pattern, the second pattern being located between adjacent first patterns, the first pattern being different from the second pattern in material property. Since the first pattern and the second pattern in the previous layer mark in the semiconductor mark according to the present disclosure are different in material property, during measurement, the first pattern and the second pattern are different in reflectivity for measurement light. Thus, the contrast of images of the first pattern and the second pattern obtained during measurement is improved, the positions and boundaries of the first pattern and the second pattern are clearly determined, and the measurement of the previous layer mark is more accurate.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a base and forming, on the base, a bit line contact region provided with a first groove; forming a first bit line contact layer in the first groove, wherein the first bit line contact layer in the first groove defines a second groove; forming a diffusion layer in the second groove, wherein the diffusion layer in the second groove defines a third groove; forming, in the third groove, a second bit line contact layer provided with a gap; and processing the diffusion layer.

Abstract: The disclosed driver and memory include: a phase driver that receives a first voltage signal, configured to output a second phase signal according to the first phase signal and the first voltage signal; a complementary phase driver includes: a first inverter for generating a complementary inverted phase signal based on a first complementary phase signal, the first phase signal and the first complementary phase signal are mutually inverted; a second inverter for receiving an output signal of the first inverter and a second voltage signal, the voltage value of the second voltage signal is smaller than that of the first voltage signal, and the second inverter is configured to be based on the first complementary inverted phase signal, and the second voltage signal outputs a second complementary phase signal. The driver of the embodiment provides the second phase signal and the second complementary phase signal.

Abstract: A semiconductor structure is provided with a test region. In test region, the semiconductor structure includes a semiconductor substrate, a plurality of bit line contact structures arranged on semiconductor substrate and a plurality of wire groups. The semiconductor structure is provided with a plurality of separate active regions extending along a first direction. In first direction, each active region is electrically connected to two bit line contact structures. The plurality of wire groups are arranged along a second direction. Each wire group includes a plurality of wires extending along a third direction. In third direction, each of two bit line contact structures for each active region is connected to respective one of two bit line contact structures for active region adjacent to said each active region by a respective one of wires, so that two wire groups of the wire groups cooperate with each other to form a conductive path.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

Abstract: Embodiments of the present application relate to the field of semiconductors, and provide a manufacturing method of a semiconductor structure and a structure thereof. The method of manufacturing a semiconductor structure includes: providing a substrate, active regions and an isolation structure; patterning the active regions and the isolation structure to form a word line trench, sidewalls of the word line trench exposing the active regions and the isolation structure; performing corner rounding at least once on the active regions and the isolation structure exposed by the sidewalls of the word line trench, such that a first height difference is formed between remaining active regions and the isolation structure, wherein the corner rounding includes: etching the isolation structure exposed by the sidewalls of the word line trench, such that a first thickness of the active regions are exposed by the isolation structure.

Abstract: Embodiments of the disclosure provide a control amplification circuit, a sensitive amplifier and a semiconductor memory. The control amplification circuit includes: a power consumption control circuit, configured to receive a power consumption control signal and output a first reference signal according to the power consumption control signal; an isolating circuit, configured to determine a control instruction signal and generate an isolation control signal according to the control instruction signal; and an amplification circuit, configured to receive the first reference signal, the isolation control signal and a signal to be processed, and process the signal to be processed based on the first reference signal and the isolation control signal to obtain a target amplified signal.

Abstract: A counter circuit includes an addition circuit including counting circuits corresponding to binary bits, a subtraction circuit and control circuits. Each counting circuit obtains a carry signal and this-time bit value according to addend signal and bit value currently output by the counting circuit, outputs the carry signal to next counting circuit, and latches the this-time bit value in response to first clock and outputs same to output terminal of the counting circuit in response to second clock. The subtraction circuit is connected to the counting circuits, obtains present subtraction counting result according to present addition counting result and subtrahend signal and outputs same in response to a first refresh instruction. Each control circuit corresponds to a counting circuit, outputs, in response to second refresh instruction, corresponding bit of the present subtraction counting result to the counting circuit to serve as the bit value output by the counting circuit.