Abstract: A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

Abstract: A system for monitoring a closed state of a cover of an exposure machine includes a servo motor, a photoelectric encoder, and a controller. A shaft of the servo motor is coaxially fixedly connected to a shaft of the cover. The photoelectric encoder is provided on the servo motor, and is configured to detect an angle of rotation of the shaft of the servo motor. The controller is connected to the servo motor and the photoelectric encoder, and is configured to control rotation of the shaft of the servo motor and determine whether the cover is in the closed state according to the angle.

Abstract: A sense amplifier includes an amplifying circuit and a voltage equalizing circuit. The amplifying circuit includes: a first P-type transistor, having a first terminal connected to a third node, a second terminal connected to a first node, and a gate connected to a first bit line; a second P-type transistor, having a first terminal connected to the third node, a second terminal connected to a second node, and a gate connected to a second bit line; a first N-type transistor, having a first terminal connected to the first node, a second terminal connected to a fourth node, and a gate connected to the first bit line; a second N-type transistor, having a first terminal connected to the second node, a second terminal connected to the fourth node, a gate connected to the second bit line. The voltage equalizing circuit is connected between the first node and the second node.

Abstract: An impedance matching circuit includes a driver circuit, a calibration circuit, a digital logic circuit, a receiving circuit and a first resistor. An output of the driver circuit is connected to the receiving circuit, and an output of the calibration circuit is connected to the first resistor. The calibration circuit is configured to cooperate with the driver circuit to perform calibration according to the impedance values of the first resistor and the receiving circuit to determine a plurality of calibration parameters obtained at different output level values. The digital logic circuit is configured to receive the plurality of calibration parameters and determine a respective target calibration parameter of each of the at least one transistor slice in the driver circuit. The driver circuit is configured to receive the target calibration parameter, and perform impedance adjustment on the at least one transistor slice according to the target calibration parameter.

Abstract: The present application provides a temperature calibration method for a semiconductor machine, including following steps: providing at least one temperature calibration sheet, the temperature calibration sheet comprising a transistor having a voltage-temperature characteristic curve corresponding to a set current; placing the temperature calibration sheet in a measurement region of the semiconductor machine; energizing the temperature calibration sheet at an energizing current being the same as the set current, and measuring a voltage of the transistor; and, obtaining a temperature of the transistor according to the voltage-temperature characteristic curve of the transistor by using the voltage as a known parameter, the temperature being a temperature of the measurement region of the semiconductor machine. The accuracy of temperature calibration is greatly improved, the performance of the semiconductor machine and the yield of the semiconductor manufacturing process are also improved.

Abstract: A method for correcting a robot is provided. The method includes: providing a correction device, wherein the correction device comprises a jig wafer; grabbing and/or transferring the jig wafer by using the robot to obtain collected data; determining, based on the collected data, whether the robot needs to be corrected; and in response to that the robot needs to be corrected, obtaining a compensation value according to the collected data, and correcting the robot based on the compensation value.

Abstract: Embodiments of the disclosure provide a system and method for adjusting an oxygen content in an FOUP. The system for adjusting the oxygen content in the FOUP includes an inflating assembly, the FOUP, a controller and a detecting assembly; the inflating assembly is connected with a gas inlet of the FOUP and configured to input an inert gas to the FOUP; the detecting assembly is connected with a gas outlet of the FOUP and configured to detect the oxygen content of the gas in the FOUP; and the inflating assembly and the detecting assembly are both connected with the controller, and the controller is configured to adjust a flow of the inert gas input from the inflating assembly to the FOUP according to the oxygen content detected by the detecting assembly.

Abstract: A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate, and forming a first sacrificial layer on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer; patterning the first sacrificial layer, and forming first intermediate pattern structures that are arranged at intervals, where a first gap is provided between two adjacent first intermediate pattern structures; forming a first spacer pad layer in the first gap, where the first spacer pad layer covers sidewalls of each of the two adjacent first intermediate pattern structures and a bottom of the first gap; removing the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer; and removing the first sacrificial dielectric layer, to form first pattern structures.

Abstract: A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.

Abstract: A compensation method and system for exposure alignment are provided. The method includes: acquiring original data of an aligned pattern, performing first-order processing on the original data to obtain first-order derivative data, obtaining a compensation value based on the original data and the first-order derivative data when exposure alignment has deviation, and compensating the exposure alignment based on the compensation value. According to the compensation method for exposure alignment, the first-order derivative data is obtained by performing first-order processing on the original data, and then the compensation value is obtained based on the original data and the first-order derivative data to compensate the exposure alignment, so that the compensation accuracy is higher, and the accuracy of exposure alignment is optimized.

Abstract: Embodiments of the present disclosure provide a forming method of a semiconductor structure and a semiconductor structure. The forming method includes: providing a base, the base includes a central region and dummy regions, and the central region includes a molding region and cutting regions; forming multiple spaced core pillars on the base; forming an initial mask layer surrounding and covering a sidewall of each core pillar on the base; removing the initial mask layers located in each cutting region to form multiple spaced mask sidewall strips in the molding region, and retaining at least one of the initial mask layers in each dummy region as a ring-shaped sidewall; removing the core pillars located in the central region and the dummy regions; and etching the base to form multiple functional structures, and etching the base to form dummy functional structures on two sides of the multiple functional structures.

Abstract: A memory chip test method includes: a mode register write command is sent to a memory chip to control a memory chip to enter a test mode of Write Clock to clock leveling (Wck2ck Leveling); a first preset time is set, and a read and write clock signal is sent to the memory chip after waiting for the first preset time; a predicted value of the Wck2ck Leveling is determined according to the first preset time and a system clock cycle; after sending the read and write clock signal and waiting for a second preset time, a test data output port of the memory chip is detected to obtain a test value; and the test value and the predicted value are compared to determine whether the memory chip is abnormal. A method for testing a Wck2ck Leveling function is provided.

Abstract: The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory. The method for manufacturing a semiconductor structure includes the following steps: providing a substrate, and forming a stabilizing layer on the substrate; forming a stabilizing structure consisting of a plurality of linear structures and grooves among the linear structures; forming a hard mask layer covering the stabilizing structure; forming a mask pattern connected to a top of the linear structure and an inner wall of the groove on the hard mask layer; and transferring the mask pattern to the substrate.

Abstract: The embodiment of the application provides a semiconductor structure and a method for forming a semiconductor structure. The method includes: a substrate structure is provided, in which the substrate structure at least including bit line structures and a plurality of landing pads, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap is formed between each two adjacent landing pads of the plurality of landing pads; and capacitive structures are formed on top surfaces of the plurality of landing pads and in the gaps.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, where a channel is formed in the base; forming a gate conductive layer, where the gate conductive layer covers a part of the channel; and forming a semiconductor doped layer, where the semiconductor doped layer fills the channel and covers the gate conductive layer, and a doping concentration of the semiconductor doped layer at a side close to a top surface of the gate conductive layer is different from a doping concentration of the semiconductor doped layer at a side away from the top surface of the gate conductive layer.

Abstract: The present disclosure provides a memory array, a memory cell, and a data read and write method thereof. Two storage nodes are provided in each memory cell of a memory array of a magnetic random access memory (MRAM), such that when one storage node in the memory cell fails, the other storage node in the memory cell can be used to write and read data.

Abstract: A method, device for checking data, an electronic device and a storage medium are provided. The method includes operations as follows. A memory array is read to obtain read data, and the read data is compressed to obtain first compressed data. The first compressed data is compared with second compressed data, the second compressed data being obtained by compressing written data corresponding to the read data. In responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data is detected, to determine whether the read data is correct. It is determined that the read data is correct if the data of the predetermined bit is consistent with the pre-stored original bit data, otherwise it is determined that the read data is incorrect.

Abstract: A storage system for reticles includes carrier devices, including reticle placing regions for placing the reticles; a storage device, storing a preset coordinate system and position information of the carrier devices in the preset coordinate system; detection devices, arranged in one-to-one correspondence with the carrier devices, where each detection device performs reticle detection on a respective carrier device, send first detection signal responsive to a reticle being placed in the reticle placing region, and send second detection signal responsive to a reticle being placed outside the reticle placing region, the detection devices are connected with the storage device, and the storage device is further configured to store reticle position information of the reticle in the preset coordinate system when receiving the first or second detection signal; and alarm devices, connected with the detection devices in one-to-one correspondence, where each alarm device implements alarm display when receiving the seco

Abstract: An oscillation period detection circuit and method, and semiconductor memory are provided. The oscillation period detection circuit includes an oscillator module, a control module, and a counting module. The oscillator module includes a target oscillator, and is configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; the control module is configured to receive the enable signal and the oscillation clock signal, and perform valid time reforming processing according to the oscillation clock signal and the enable signal to determine a target time; the counting module is configured to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number. The oscillation period of the target oscillator is calculated according to the target time and the target period number.

Abstract: A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.