Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same, and relates to the field of semiconductor technologies. The manufacturing method includes: providing a substrate and forming a film layer stack structure thereon; etching the film layer stack structure to form a first region containing a through hole through which the substrate is exposed and a second region containing a hole section through which the substrate is not exposed; and patterning and etching the second region to remove the film layer stack structure within the second region.

Abstract: The present application provides a semiconductor structure and a forming method thereof. The method of forming the semiconductor structure includes: providing a semiconductor chip and a substrate; forming, on the substrate, a first covering film covering a metal pad and a surface of the substrate, a plurality of up-narrow and down-wide openings being formed in the first covering film, and a bottom of each of the up-narrow and down-wide openings correspondingly exposing a surface of the metal pad; and flipping the semiconductor chip onto the substrate, such that a solder bump on a metal pillar is correspondingly located in the up-narrow and down-wide opening, and the solder bump fill the up-narrow and down-wide opening.

Abstract: The embodiment of the application provides a semiconductor structure and a method for forming a semiconductor structure. The method includes: a substrate structure is provided, in which the substrate structure at least including bit line structures and a plurality of landing pads, each of the plurality of landing pads is formed around a respective one of the bit line structures and covers a part of the respective one of the bit line structures, and a gap is formed between each two adjacent landing pads of the plurality of landing pads; and capacitive structures are formed on top surfaces of the plurality of landing pads and in the gaps.

Abstract: A method, device for checking data, an electronic device and a storage medium are provided. The method includes operations as follows. A memory array is read to obtain read data, and the read data is compressed to obtain first compressed data. The first compressed data is compared with second compressed data, the second compressed data being obtained by compressing written data corresponding to the read data. In responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data is detected, to determine whether the read data is correct. It is determined that the read data is correct if the data of the predetermined bit is consistent with the pre-stored original bit data, otherwise it is determined that the read data is incorrect.

Abstract: A semiconductor structure includes a chip structure and a sealing structure disposed on a substrate of the semiconductor structure. The sealing structure includes a metal wall body and a blocking wall body located on a top of the metal wall body, and the metal wall body and the blocking wall body both are disposed around the chip structure.

Abstract: A refresh address generation circuit includes: a refresh control circuit and an address generator. The refresh control circuit receives multiple first refresh commands in sequence and performs multiple first refresh operations accordingly, outputs a first clock signal when the number of first refresh operations is less than m, and outputs a second clock signal when the number of first refresh operation is equal to m. The address generator is coupled to the refresh control circuit, and configured to prestore a first address and receive the first clock signal or the second clock signal, and during each first refresh operation, output an address to be refreshed in response to the first clock signal and change the first address in response to the second clock signal. The address to be refreshed includes a first address and a second address with the lowest bit opposite to that of the first address.

Abstract: An oscillation period detection circuit and method, and semiconductor memory are provided. The oscillation period detection circuit includes an oscillator module, a control module, and a counting module. The oscillator module includes a target oscillator, and is configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; the control module is configured to receive the enable signal and the oscillation clock signal, and perform valid time reforming processing according to the oscillation clock signal and the enable signal to determine a target time; the counting module is configured to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number. The oscillation period of the target oscillator is calculated according to the target time and the target period number.

Abstract: A power supply circuit and a memory are provided. The power supply circuit includes: a voltage generation module, configured to provide an initial voltage signal; a first power supply module, configured to provide a power reference voltage based on the initial voltage signal; an amplification module, configured to generate and output a first power voltage based on the power reference voltage; a first power network, configured to supply power to at least one function module connected to the first power network; a second power supply module, a second power network and a voltage control module. The second power supply module is configured to provide a second power voltage for the second power network based on the initial voltage signal.

Abstract: A semiconductor structure and a manufacturing method are provided. The semiconductor structure includes: a substrate having a bit line extending along a first direction; a semiconductor channel located on the bit line; a semiconductor doping layer located on the side of the bit line, wherein the top surface of the semiconductor doping layer is connected to the semiconductor channel contact; a word line extending in the second direction, encircling part of the semiconductor channel, and the bottom surface of the word line is higher than the top surface of the bit line; a word line dielectric layer located between the word line and the semiconductor channel; an isolation layer located between the word line and the bit line and between the word line and the semiconductor doping layer. The device and method improve the prior weak electrical conductivity between the bit line structure and the active structure.

Abstract: The present disclosure relates to the technical field of semiconductors, and provides a vacuum system, a low-pressure vacuum process device, and a cutoff member. The vacuum system includes: a vacuum pump; an exhaust pipeline, wherein one end of the exhaust pipeline is used to communicate with a chamber to be evacuated, and the other end of the exhaust pipeline communicates with the vacuum pump; and a cutoff member, wherein the cutoff member is connected to the exhaust pipeline, the cutoff member includes a filter portion and a carrier portion, the filter portion includes a passage, the carrier portion includes an accommodation groove, and the passage communicates with the accommodation groove.

Abstract: The present disclosure relates to a fixture, the fixture is a fixture for a semiconductor etching machine, and the fixture includes: a support mechanism, configured to be arranged on an outer base of an electrostatic chuck of the semiconductor etching machine; a cleaning mechanism, being rotatably arranged on the support mechanism; and at least one cleaning unit, being arranged on the cleaning mechanism.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure, and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, where a channel is formed in the base; forming a gate conductive layer, where the gate conductive layer covers a part of the channel; and forming a semiconductor doped layer, where the semiconductor doped layer fills the channel and covers the gate conductive layer, and a doping concentration of the semiconductor doped layer at a side close to a top surface of the gate conductive layer is different from a doping concentration of the semiconductor doped layer at a side away from the top surface of the gate conductive layer.

Abstract: A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a substrate, bit line structures and isolation walls located on side walls of the bit line structures, and capacitor contact holes. In the substrate, conductive contact regions are arranged. The conductive contact regions are exposed from the substrate. A plurality of discrete bit line structures are located on the substrate. Each of the isolation walls includes at least one isolation layer and a gap between the isolation layer and the bit line structure. Each of the capacitor contact holes is constituted by a region surrounded by the isolation walls between the adjacent bit line structures. The capacitor contact holes expose the conductive contact regions. A top width of the capacitor contact holes is larger than a bottom width thereof in a direction parallel to an arrangement direction of the bit line structures.

Abstract: A method for manufacturing the semiconductor structure includes: a substrate is provided; isolation structures having a first depth are formed in the substrate; word line structures having a second depth are formed in the substrate, where part of the word line structures are formed in respective ones of the isolation structures, and the second depth is less than the first depth; the isolation structures are etched in a direction perpendicular to the substrate to form a first trench having a third depth in each isolation structure; and a first insulating layer covering the word line structures and the first trenches is formed on the substrate to form an air gap structure in each isolation structure.

Abstract: A method for forming a capacitor via includes: providing a to-be-processed wafer, the to-be-processed wafer including a substrate and a first dielectric layer and a first mask layer that are sequentially formed on a surface of the substrate; etching the first mask layer according to a compensated first etching parameter, to form a first patterned layer extending in a first etching direction; sequentially forming a second dielectric layer and a second mask layer on a surface of the first patterned layer; etching the second mask layer and the second dielectric layer according to a compensated second etching parameter, to form a second patterned layer extending in a second etching direction; and etching the first dielectric layer with the first patterned layer and the second patterned layer together as a capacitor pattern, to form a capacitor via.

Abstract: Some embodiments of the present application disclose a polishing liquid supply system. In the present application, the polishing liquid supply system includes: a polishing liquid preparation device, a cleaning liquid supply device and a filtering device, and further includes a supply pipeline connected with the polishing liquid preparation device and the filtering device and a cleaning pipeline connected with the cleaning liquid supply device and the filtering device. The polishing liquid preparation device is configured to prepare a polishing liquid and convey the prepared polishing liquid to the filtering device through the supply pipeline. The filtering device is configured to filter the polishing liquid and convey the filtered polishing liquid to a polishing device connected with the filtering device. The cleaning liquid supply device is configured to convey a cleaning liquid to the filtering device through the cleaning pipeline.

Abstract: Embodiments provide an input buffer circuit and a semiconductor memory, a compensation subcircuit is provided between an input terminal of the input buffer circuit and a first terminal of a load subcircuit, a current of an output terminal of the input buffer circuit is increased, and voltage variation of the input terminal can be transmitted to the output terminal in time, such that the output terminal can timely receive the voltage variation of the input terminal, thereby avoiding distortion of an output signal, solving a problem of signal attenuation for the input buffer circuit, improving sensitivity of the input buffer circuit, and preventing negative effects from being caused to transmission of commands inside a system.

Abstract: The present disclosure provides a method and an apparatus for detecting a data path, and a storage medium, relates to the technical field of semiconductors, and is applied to a process of detecting a data path of a semiconductor integrated circuit. The method for detecting a data path includes: disconnecting, by a detection apparatus, a connection between a global data line and a local data line in the data path, writing test data into the global data line in the data path via the data path through a write port of the data path, reading, by the detection apparatus, target data of the global data line under a preset condition, and further detecting a defect of the data path according to the test data and the target data.

Abstract: A semiconductor structure and a chip are provided. The semiconductor structure includes: a first active area and a second active area extending along a first direction and having a first width in a second direction; a first WordLine (WL) drive transistor group including two gate dielectric areas connected to the first active area; a second WL drive transistor group including two gate dielectric areas connected to the first active area; a third WL drive transistor group including two gate dielectric areas connected to the second active area; and a fourth WL drive transistor group including two gate dielectric areas connected to the second active area. Each of the gate dielectric area extends along the second direction and has a second width in the first direction.

Abstract: A semiconductor structure includes a substrate, an isolation structure formed in the substrate, and a word line including a first convex portion and a second convex portion. The first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.