Abstract: A power supply circuit includes: power supplying module configured to provide DC voltage; transformer module including primary-side first winding connected to power supplying module and secondary-side winding coupled to primary-side first winding; switch module having one end connected to primary-side first winding and the other end connected to grounding terminal; control module connected to switch module, where control module is configured to control switch module to have different switching frequencies and/or different turning-off times, to enable first pulse voltages with different duty cycles to be formed on primary-side first winding, and second pulse voltages with different duty cycles to be subsequently generated on secondary-side winding; and voltage conversion module having input terminal connected to secondary-side winding and output terminal connected to voltage output terminal of power supply circuit, where voltage conversion module is configured to convert second pulse voltages with different du

Abstract: Provided is a manufacturing method of a semiconductor structure, including: providing a substrate; forming a first mask layer having a first mask pattern on the substrate, and etching the substrate by using the first mask layer as a mask to form active regions; forming several discrete bitlines on the active regions; forming a sacrificial layer between adjacent bitlines; forming a second mask layer having a second mask pattern on the sacrificial layer, the first mask pattern and the second mask pattern being complementary to each other; and etching the sacrificial layer by using the second mask layer and the bitlines as masks to form a plurality of contact structures. The embodiment of the present disclosure is beneficial to reducing the manufacturing cost of the semiconductor structure.

Abstract: A method for preparing a capacitor contact structure of a memory device includes providing a substrate, forming a plurality of bit line structures arranged in parallel and at intervals on the substrate, and the bit line structures extending along a first direction; forming conducting layer structures between adjacent bit line structures, upper surfaces of which are lower than upper surfaces of the bit line structures; forming sacrificial layers on the conducting layer structures; forming a plurality of isolation trenches arranged in parallel and at intervals in the sacrificial layer, the isolation trenches extend along a second direction, and the second direction intersects the first direction; forming isolation dielectric layers in the isolation trenches; and removing the sacrificial layer based on the bit line structure and the isolation dielectric layer to form grooves between adjacent bit line structures and between adjacent isolation dielectric layers, the grooves expose the conducting layer structures.

Abstract: An embodiment of the application provides a method for forming a semiconductor structure. The semiconductor structure includes a first region and a second region. The method includes the following steps: providing a base, an insulating layer, and a mask layer that are stacked in sequence, where the first region has at least one trench penetrating the mask layer and the insulating layer, and the mask layer has an upper surface in the second region higher than that in the first region; forming a first protection layer, where an upper surface and a sidewall of the mask layer in the first region are covered with the first protection layer; after the first protection layer is formed, removing the mask layer in the second region; subsequent to removal of the mask layer in the second region, removing the first protection layer; and removing the mask layer in the first region.

Abstract: The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device. The method for manufacturing a semiconductor device includes: providing a substrate; forming a plurality of first structures extending in a first direction on the substrate; forming a sacrificial layer on sidewalls of the first structures; forming an outer spacer layer on a sidewall of the sacrificial layer; removing part of the outer spacer layer to obtain a patterned outer spacer layer that exposes part of the sacrificial layer; and removing the sacrificial layer to form air gaps between the patterned outer spacer layer and the first structures.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: providing a base, wherein the base includes an active region and a shallow trench isolation structure separating the active region, a word line trench is formed in the base, and the word line trench exposes a part of the active region and the shallow trench isolation structure; forming a first intermediate structure in the word line trenches, wherein the first intermediate structure covers side walls and a bottom wall of the word line trench, a first trench is formed in the first intermediate structure, the first intermediate structure includes a sacrificial structure, and the sacrificial structure includes a horizontal portion; and removing the horizontal portion of the sacrificial structure, and closing the first trench, and forming an air chamber.

Abstract: A method for forming a micro bump includes the following operations. A chip at least including a silicon substrate and a Through Silicon Via (TSV) penetrating through the silicon substrate is provided. A conductive layer having a first preset size in a first direction is formed in the TSV, the first direction being a thickness direction of the silicon substrate. A connecting layer having a second preset size in the first direction is formed on a surface of the conductive layer in the TSV, where a sum of the first preset size and the second preset size is equal to an initial size of the TSV in the first direction. The silicon substrate is processed to expose the connecting layer, for forming a micro bump corresponding to the TSV.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a semiconductor body, bit lines and word lines. The semiconductor body includes a substrate and an isolation structure positioned above the substrate and configured to isolate a plurality of active regions, part of each of the active regions being formed from the substrate. The bit lines are positioned in the substrate and are connected to the active regions. The word lines intersect with the active regions and surround the active regions. The substrate is Silicon On Insulator (SOI) substrate.

Abstract: An installation fixture for needle is used to install needles of an electrostatic chuck, and includes: a positioning tray, detachably disposed on an outer base of the electrostatic chuck, the positioning tray being provided with installation holes, and the installation holes corresponding to installation positions of the needles of the electrostatic chuck; and an installation fixture, detachably installed in the installation hole to adjust the installation depth of the needle.

Abstract: A semiconductor memory includes a main memory area and a tag memory area. A plurality of memory groups are set in the main memory area and a plurality of flag bits are set in the tag memory area. Each of the plurality of memory groups has a corresponding relationship with one of the plurality of flag bit. The flag bit is at least configured to indicate whether at least one memory cell in the memory group has a specific state. The specific state includes an occupied state.

Abstract: A method for forming a memory device includes: providing a substrate including at least word line structures and active regions, and a bottom dielectric layer and bit line contact layers that are on a top surface of the substrate; part of the bit line contact layers are etched to form bit line contact layers at different heights; conducting layers are formed, top surfaces of the conducting layers being at different heights in a direction perpendicular to an extension direction of the word line structure, and the top surfaces of the conducting layers being at different heights in the extension direction of the word line structure; top dielectric layers are formed; and etching is performed to form separate bit line structures.

Abstract: The present disclosure provides an apparatus and a method for transferring a wafer, and an apparatus for controlling transferring a wafer. The apparatus for transferring a wafer includes a transfer chamber, at least one process chamber, a first detection unit, and a control unit, wherein the transfer chamber is provided therein with a transfer unit; the at least one process chamber is in connect with the transfer chamber, and a chamber door is provided at a connect position; the first detection unit includes a first transmit end and a first receive end, the first transmit end is provided on one of the transfer unit and the chamber door, and the first transmit end is provided on the other one of the transfer unit and the chamber door.

Abstract: A method for checking a Design for Test (DFT) circuit includes: transmitting a control signal to the DFT circuit to determine test mode signals output by the DFT circuit, with the DFT circuit being configured to sequentially select multiple address latches according to the control signal to output the test mode signals; analyzing the test mode signals to determine whether the multiple address latches in the DFT circuit have an error; and outputting a simulation result report.

Abstract: Provided is a Plasma Induced Damage (PID) test structure and a semiconductor test structure, including: a gate structure, including a gate layer; a covering dielectric layer, located on a surface of the gate layer; a metal layer structure, located on a surface of the covering dielectric layer, the metal layer structure including at least one metal layer; and an extraction electrode, electrically connected with the gate layer via a conductive structure.

Abstract: A fault isolation analysis method includes: providing a package structure in which there is an electrical fault; detecting whether the electrical fault is in interconnecting wires, and if the electrical fault is in the interconnecting wires, determining that the electrical fault is caused by the interconnecting wire; and if the electrical fault is not in the interconnecting wires, breaking the interconnecting wires to electrically isolate the chip structure from the substrate, then detecting whether the electrical fault is in the structure, and if the electrical fault is able to be detected, determining that the electrical fault is caused by the substrate, or if the electrical fault is not able to be detected, determining that the electrical fault is caused by the chip structure.

Abstract: A method for predicting an inclination angle of an etched hole can include operations as follows. A preset change range of an etching rate of an etching device for an object to be etched on a surface of a monitored sample in different operation stages is determined. An etching rate change curve of the etching device for the object to be etched on the surface of a monitored sample in a current operation stage is acquired. When the etching rate change curve exceeds the preset change range, it is determined that an inclination angle of an etched hole of an etched product currently etched by the etching device exceeds a preset angle.

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The method includes: providing a substrate, wherein the substrate includes a word line region, a bit line region, and a capacitive region arranged adjacently; forming a first stacked structure that covers a surface of the substrate, wherein the first stacked structure includes a first sacrificial layer located on the surface of the substrate and a first semiconductor layer located on a surface of the first sacrificial layer; forming a second stacked structure that covers a surface of the first stacked structure, wherein the second stacked structure includes a second sacrificial layer located on the surface of the first stacked structure and a second semiconductor layer located on a surface of the second sacrificial layer; and performing an ion implantation on the first semiconductor layer and the second semiconductor layer.

Abstract: A method for temperature control includes: acquiring the present temperature of a reaction window in a process chamber of a semiconductor machine; comparing the present temperature with the preset temperature to acquire a comparison result; and adjusting the exhaust amount of an exhaust passage of the process chamber based on the comparison result to control the temperature of the reaction window.

Abstract: The present disclosure provides a memory bank and a memory, relating to the technical field of semiconductors. The memory bank includes: multiple memory arrays arranged along a first direction, configured to store data and check codes, and each of the memory arrays being divided into at least two array units; multiple read-write control circuits, in one-to-one correspondence to the memory arrays, and the read-write control circuit being configured to write the data and the check codes to a corresponding memory array or read the data and the check codes from the corresponding memory array; the read-write control circuit being electrically connected to the array units through different data signal lines, and the read-write control circuit being configured to access only one of the array units in the corresponding memory array at a time; and multiple error checking and correcting units, electrically connected to the multiple read-write control circuits.

Abstract: The data receiving circuit includes: a first amplification module configured to: receive a data signal, a first reference signal, and a second reference signal; and when an enable signal is at a first level, in response to a sampling clock signal and on a basis of a feedback signal, select the data signal and the first reference signal for first comparison and output a first signal pair, or select the data signal and the second reference signal for second comparison and output a second signal pair; and a second amplification module configured to receive output signals of the first amplification module as an input signal pair, perform amplification processing on a voltage difference of the input signal pair.