Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Data receiving circuit, data receiving system and storage device
    Patent number: 12170129
    Abstract: A data receiving circuit includes: a first amplification module configured to receive a data signal and a reference signal, compare the data signal and the reference signal in response to a first sampling clock signal, and output a first voltage signal and a second voltage signal; a decision feedback control module configured to generate a second sampling clock signal in response to the enable signal; a decision feedback equalization module configured to, when the enable signal is in a first level value interval, perform decision feedback equalization in response to the second sampling clock signal and stop performing the decision feedback equalization when the enable signal is in a second level value interval; and a second amplification module configured to process the first voltage signal and the second voltage signal and output the first output signal and the second output signal.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: December 17, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Feng Lin
  • Semiconductor structure, formation method thereof and memory
    Patent number: 12171094
    Abstract: Embodiments of the present application disclose a semiconductor structure, a formation method thereof and a memory. The semiconductor structure includes: a substrate; a channel located in the substrate, the channel being configured to form a gate structure; and a convex portion arranged on an inner wall of the channel. The embodiments of the present application can increase a channel length and solve a short-channel effect.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: December 17, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Wei Wan
  • Method for preparing semiconductor structure and semiconductor structure
    Patent number: 12170201
    Abstract: A method for preparing a semiconductor structure, and a semiconductor structure are provided. In a prepared first pattern structure, a thickness of a first insulating layer is equal to a thickness of a second insulating layer, and a thickness of a third insulating layer is equal to a thickness of a fourth insulating layer.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: December 17, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Tao Liu, Sen Li
  • Manufacturing method and measurement method of semiconductor structure, andsemiconductor structure
    Patent number: 12170232
    Abstract: The present disclosure provides a manufacturing method and measurement method of a semiconductor structure, and a semiconductor structure, relating to the technical field of semiconductors. The manufacturing method of a semiconductor structure includes: providing a base including multiple gate trenches; and forming a gate structure in each of the gate trenches, wherein each gate structure includes a barrier layer and a conductive layer, the barrier layer and the conductive layer are sequentially stacked, the barrier layer is in contact with a bottom wall of each of the gate trenches, and a material of the conductive layers includes polysilicon.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: December 17, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Fangfang Wang
  • Semiconductor structure and manufacturing method thereof
    Patent number: 12165919
    Abstract: A manufacturing method of a semiconductor structure includes: a substrate is provided; and an intermediate layer is formed on the substrate, an I-shaped member and a wall-shaped member are formed in the intermediate layer, a top surface of the wall-shaped member is not lower than a top surface of the I-shaped member, and a bottom surface of the wall-shaped member is not higher than a bottom surface of the I-shaped member.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Mengmeng Wang, Hsin-Pin Huang
  • Semiconductor devices and preparation methods thereof
    Patent number: 12167588
    Abstract: A preparation method for a semiconductor device includes: providing a semiconductor substrate, the semiconductor substrate having shallow trenches and active regions defined by the shallow trenches, the active regions extending in a first direction; forming isolation layers in the first direction at interfaces between the shallow trenches and the active regions, the isolation layers and the active regions being inverse types to each other; forming shallow trench isolation structures in the shallow trenches; and forming word-line structures, the word-line structures extending in a second direction and sequentially passing through the shallow trench isolation structures and the active regions.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Yukun Li
  • Semiconductor structure and method for preparing semiconductor structure
    Patent number: 12166028
    Abstract: A semiconductor structure and a method for preparing the semiconductor structure are provided. The semiconductor structure includes a substrate, a storage node contact and a capacitor isolating structure. The storage node contact is located on the substrate, and the capacitor isolating structure is located on the substrate, covers a side wall of the storage node contact and includes a first air gap.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiao Zhu
  • Method for manufacturing semiconductor device and semiconductor device
    Patent number: 12165913
    Abstract: A method for manufacturing a semiconductor device includes: forming an isolating layer on a surface of a substrate; forming a groove on the isolating layer, where the groove penetrates the isolating layer; forming a protection layer in the groove and on the isolating layer; forming a dielectric layer on the protection layer; and forming a contact hole, where the contact hole penetrates the protection layer and the dielectric layer to the surface of the substrate, respectively. The method for manufacturing the semiconductor device according to the present invention can be used not only in chemical vapor deposition but also in a process of a metal wire of a short-circuit in physical vapor deposition.
    Type: Grant
    Filed: October 3, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Suli Wang
  • Semiconductor device and oxygen removal method thereof
    Patent number: 12165883
    Abstract: The present invention discloses a semiconductor device and an oxygen removal method thereof. The semiconductor device comprises: a process cavity, an oxygen removal pipe and an oxygen detection device, wherein the oxygen detection device comprises an oxygen detection pipe, a switching ball valve and an oxygen sensor; the oxygen detection pipe comprises a first pipe, a second pipe and a third pipe which are arranged in parallel and all connected to the oxygen removal pipe and the switching ball valve; the oxygen sensor is arranged on the third pipe; and, the switching ball valve is constructed in such a way that the switching ball valve communicates the first pipe with the second pipe in an oxygen removal stage and communicates the first pipe with the third pipe in an oxygen detection stage.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Min Zuo
  • Method and apparatus for identifying probe abnormity, storage medium, and electronic device
    Patent number: 12163848
    Abstract: A method for identifying the probe abnormality includes: obtaining current temperature data of a plurality of probes, and calculating a temperature difference value between every two pieces of current temperature data; comparing the temperature difference value with a preset temperature difference, and when the temperature difference value exceeds the preset temperature difference, determining that at least one of the plurality of probes is abnormal; and heating the device to a preset temperature, and determining an abnormal probe from the plurality of probes.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhaoyun Dai
  • Manufacturing method for semiconductor structure
    Patent number: 12165910
    Abstract: A manufacturing method for a semiconductor structure includes: patterning and etching a semiconductor substrate to form a concave region; forming a first protective layer on a surface of the semiconductor substrate, the surface of the semiconductor substrate being a surface of a non-etched region except the concave region; forming an isolation structure in the concave region; and removing the first protective layer on the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chao Wu
  • Semiconductor transistor structure and manufacturing method
    Patent number: 12166070
    Abstract: The present application discloses a semiconductor transistor structure, which includes: a substrate formed with a well region of a first conductive type, a gate structure being disposed on the substrate; a source/drain region of a second conductive type disposed in the well region of the first conductive type, the source region and the drain region being located on two sides of the gate structure respectively; a contact hole formed at a position corresponding to the source/drain region; and a conductive metal filled in the contact hole, the bottom of the contact hole being implanted with impurity ions for decreasing the contact resistance of the contact hole, and the impurity ion concentration at a peripheral region where the bottom of the contact hole comes into contact with the source/drain region being lower than the impurity ion concentration at a middle region.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jifeng Tang
  • Method for manufacturing semiconductor structure and semiconductor structure
    Patent number: 12165879
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method for manufacturing a semiconductor structure includes: forming a conductive layer, a protective layer, and a mask layer in sequence on the substrate, the mask layer including a first pattern facing the first region and a second pattern facing the second region; forming a restriction pattern located in the second region by etching the protective layer using the mask layer as a mask; and forming contact pads located in the first region and connecting wires located in the second region on the conductive layer by etching the conductive layer using the mask layer as a mask.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xinman Cao, Jun Xia, Zhongming Liu, Shijie Bai
  • Semiconductor structure and a manufacturing method thereof
    Patent number: 12166133
    Abstract: A semiconductor structure includes: a substrate; a gate structure located on the substrate, wherein the gate structure comprises a first conductive layer, a barrier layer and a second conductive layer which are stacked in sequence; wherein the first conductive layer includes a first polysilicon layer, a first metal layer and a second polysilicon layer, wherein the first polysilicon layer is adjacent to the substrate and the second polysilicon layer is contiguous to the barrier layer; and wherein the first metal layer is located between the first polysilicon layer and the second polysilicon layer. The gate structure of the embodiments of the application has a straight profile and an excellent electrical performance.
    Type: Grant
    Filed: November 25, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qiang Long
  • Mask structure, semiconductor structure and manufacturing method
    Patent number: 12167584
    Abstract: A method for manufacturing a mask structure includes: patterning a sacrificial layer and a second dielectric layer, so as to form pattern structures each including a first pattern and a second pattern, and a width of a lower portion of the pattern structures is less than a width of a upper portion of the pattern structures; forming an initial mask pattern on sidewalls of each of the plurality of pattern structures; filling a first filling layer between adjacent initial mask patterns located on the sidewalls of different pattern structures; removing the second patterns and the initial mask pattern located on sidewalls of each of the plurality of second patterns; removing the first filling layer and the first patterns, so as to form first mask patterns; and forming second mask patterns on the first mask patterns.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Jun Xia, Penghui Xu, Tao Liu, Sen Li, Kangshu Zhan
  • Array structure of capacitors, method for manufacturing array structure of capacitors, and dynamic random access memory
    Patent number: 12167585
    Abstract: An array structure of capacitors are provided. The array structure of capacitors includes a substrate and a first connection pad, a second connection pad, a first capacitive structure and a second capacitive structure that are disposed on the substrate. The first capacitive structure is disposed outside the second capacitive structure and adjacent to an edge of the substrate. The bottom surface of the first capacitive structure towards the substrate and the top surface of the first connection pad are disposed at intervals.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sen Li, Qiang Wan, Tao Liu, Penghui Xu
  • Interconnection structure and manufacturing method thereof and semiconductor structure
    Patent number: 12165967
    Abstract: The present disclosure provides an interconnection structure and a manufacturing method thereof and a semiconductor structure, and relates to the technical field of semiconductors. The interconnection structure includes a substrate, a dielectric layer arranged on the substrate and an insulation layer, wherein a plurality of wires are arranged in the dielectric layer at intervals; a recess is arranged in a portion, between adjacent wires, of the dielectric layer, and a bottom of the recess exposes a surface of the substrate; and the insulation layer includes an extension portion extending into the recess, and a gap is arranged between the extension portion and the substrate.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Delong Zhu
  • Method of manufacturing semiconductor structure and semiconductor structure
    Patent number: 12167589
    Abstract: The present disclosure discloses a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method includes: providing a base, active regions arranged at intervals along a first direction being arranged in the base; forming, on the base, bit line structures arranged at intervals; forming a contact structure between two adjacent ones of the bit line structures; forming a barrier structure on the contact structure, the barrier structures being arranged in correspondence with and connected to the bit line structure, and a first recess being formed between any adjacent barrier structures; and forming a conductive structure in the first recess, the conductive structure including a protective layer and a conductive portion, and the protective layer wrapping a sidewall and a bottom wall of the conductive portion.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Guangji Li
  • Semiconductor structure and method for manufacturing semiconductor structure
    Patent number: 12166032
    Abstract: A semiconductor structure includes a substrate, a gate dielectric layer and a conductive layer that are stacked, and the gate dielectric layer is located between the substrate and the conductive layer. The substrate includes a semiconductor substrate and an insulating substrate which are arranged on the same layer. The conductive layer includes: a gate conductor layer, a projection of which on the substrate covers the semiconductor substrate, and an external connecting layer, a projection of which on the substrate covers the insulating substrate. A groove is formed on a bottom surface, towards the substrate, of the external connecting layer and the groove is filled with an insulator.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ching-Lun Ma
  • Base die with error checking and correction , memory system, and semiconductor structure
    Patent number: 12164374
    Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase.
    Type: Grant
    Filed: May 1, 2022
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning