Abstract: A semiconductor structure includes a substrate, a gate dielectric layer and a conductive layer that are stacked, and the gate dielectric layer is located between the substrate and the conductive layer. The substrate includes a semiconductor substrate and an insulating substrate which are arranged on the same layer. The conductive layer includes: a gate conductor layer, a projection of which on the substrate covers the semiconductor substrate, and an external connecting layer, a projection of which on the substrate covers the insulating substrate. A groove is formed on a bottom surface, towards the substrate, of the external connecting layer and the groove is filled with an insulator.

Abstract: A method for forming an ultra-shallow junction includes the following operations: providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, providing a dopant and implanting the dopant into the epitaxial layer and a part of the semiconductor substrate, and removing the epitaxial layer, to form the ultra-shallow junction.

Abstract: A layout method for an integrated circuit includes the following steps: providing a layout, the layout including a first element region and a second element region, a spacing region being provided between the first element region and the second element region; and detecting whether a width of the spacing region is less than a preset width, and if yes, marking at least one of the first element region, the second element region and the spacing region, the preset width being a minimum width meeting a requirement, wherein the requirement is to fill the spacing region with at least one dummy pattern. A layout apparatus employing the layout method for the integrated circuit can quickly and accurately position a poorly-placed element region in the layout, improve the layout efficiency and layout precision of the integrated circuit, and lay a foundation for improving photolithography quality.

Abstract: Provided are a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes: a through silicon via and a shielding structure disposed at an outer side of the through silicon via, in which the shielding structure includes at least two non-closed annular shielding layers surrounding the through silicon via and at least one conductive plug configured to connect two adjacent ones of the non-closed annular shielding layers; the at least two non-closed annular shielding layers and the at least one conductive plug are alternately distributed along an extending direction of the through silicon via and sequentially connected to form a conductive path, and current flow directions in two adjacent ones of the non-closed annular shielding layers in the conductive path are opposite.

Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. In the semiconductor structure, a side of a film layer structure facing away from a substrate is provided with a wiring layer, a side of the substrate facing away from the film layer structure is provided with a connecting hole extending to the wiring layer, and an insulating layer is arranged on a hole wall of the connecting hole. A barrier ring is arranged on the insulating layer, a center line of the barrier ring is arranged collinearly with a center line of the connecting hole, and diffusibility of the barrier ring is less than diffusibility of the wiring layer. A connecting post joined to the wiring layer is arranged in the connecting hole.

Abstract: A clock circuit includes at least two first driving circuits and a plurality of discrete first wires located between adjacent first driving circuits, the adjacent first driving circuits are connected through at least one first wire and at least two second wires, the first driving circuits are connected with the second wires, all of the first wires connected between two second wires are connected in series with each other, the first wires are located on a first metal layer, the second wires are located on a second metal layer, and the second metal layer is above the first metal layer.

Abstract: A data writing method includes: receiving a first writing command, and selecting a target bank and a target column address according to the first writing command, data corresponding to the first writing command being first test data; writing the first test data into the target column address of the bank selected according to the first writing command, and latching the first test data on an address bus during the writing at least until a second writing command is executed; receiving the second writing command, and reselecting the target bank and the target column address according to the second writing command; and writing the first test data latched on the address bus into a reselected target column address of a reselected target bank.

Abstract: Embodiments provide a method for fabricating a memory and a memory. This method includes: providing a substrate, the substrate being internally provided with a plurality of active areas, and each of the plurality of active areas including a first contact region and a second contact region; forming a plurality of bit lines on the substrate, each of the plurality of bit lines being connected to at least one of the first contact regions; forming an isolation layer on each of the plurality of bit lines, the isolation layer covering each of the plurality of bit lines and the substrate, the isolation layer being further provided with a plurality of filling holes corresponding to the plurality of second contact regions one to one; etching the isolation layer and the substrate along the plurality of filling holes, to fill in the plurality of second contact regions.

Abstract: Embodiments provide a control circuit and a semiconductor memory. The control circuit includes a bias switching circuit and a first logic gate circuit. The first logic gate circuit includes at least one target transistor. A substrate of one of the at least one target transistor is connected to an output terminal of the bias switching circuit. The first logic gate circuit has a first speed mode and a second speed mode. A transmission speed of the first speed mode is less than a transmission speed of the second speed mode. The bias switching circuit is configured to: receive a target signal, and output a target bias voltage, to increase a threshold voltage of the target threshold. The enabled state of the target signal represents that the first logic gate circuit is in the first speed mode.

Abstract: An anti-fuse structure includes: a first unit including a first selection transistor, a first anti-fuse (AF) cell and a second AF cell; and a second unit including a second selection transistor, a third AF cell and a fourth AF cell. The first unit and second unit share an active region, which is provided with a first extension part and a second extension part which are independent of each other at a first side, and provided with a third extension part and a fourth extension part which are independent of each other at a second side, the first side being opposite to the second side. The first AF cell is arranged at the first extension part, the second AF cell is arranged at the second extension part, the third AF cell is arranged at the third extension part, and the fourth AF cell is arranged at the fourth extension part.

Abstract: Disclosed is a method for manufacturing a contact hole, a semiconductor structure and electronic equipment. The method includes: forming a mask layer on an upper end face of a first oxide layer of the semiconductor structure, and exposing a pattern of a target contact hole on the mask layer; exposing a portion, corresponding to a target contact hole, of an upper end face of a contact layer and a portion, corresponding to the target contact hole, of an upper end face of an upper layer structure; depositing a second insulation layer on an etched surface, and depositing a second oxide layer on the second insulation layer; and removing portions, above the upper end face of the first oxide layer, of the second insulation layer and the second oxide layer, and removing a part of the contact layer, and exposing an upper end face of a zeroth layer contact.

Abstract: The present application relates to a capacitor device and a manufacturing method thereof, and a memory. forming a first capacitor structure on a substrate, includes: a first capacitor dielectric layer, a first upper electrode, a plurality of first lower electrodes arranged at intervals; the first capacitor dielectric layer at least covers sidewalls of the first lower electrodes, and the first upper electrode fills up gaps at an outer side of the first capacitor dielectric layer; forming a second capacitor structure on the first capacitor structure, the second capacitor structure includes a second capacitor dielectric layer, a second upper electrode, and a plurality of second lower electrodes arranged at intervals; the second lower electrodes are of a U-shaped structure, bottoms of the second lower electrodes are in contact with tops of the first lower electrodes, the second capacitor dielectric layer is at least located on surfaces of the second lower electrodes.

Abstract: A manufacturing method for a semiconductor structure includes: a substrate is provided, the substrate including a first region and a second region; a dielectric layer is formed on the substrate; a first diffusion film layer having a first metal oxide layer is formed on the dielectric layer; the first diffusion film layer corresponding to the second region is removed; a second diffusion film layer is formed on the dielectric layer corresponding to the second region, the second diffusion film layer including a second metal oxide layer interfacing with the dielectric layer; and an annealing treatment is performed to diffuse a first metal element in the first metal oxide layer into the dielectric layer corresponding to the first region and diffuse a second metal element in the second metal oxide layer into the dielectric layer corresponding to the second region.

Abstract: A method for manufacturing a semiconductor structure includes: providing a base, in which a plurality of bit lines extending in a first direction and a groove located between two adjacent ones of the bit lines are provided on the base; forming an initial contact layer and an initial protection layer filling the groove, in which the initial contact layer is in contact with the base, the initial protection layer is located on the initial contact layer; patterning the initial contact layer and the initial protection layer to form contact layers that are discrete from each other and protection layers that are discrete from each other; and forming a dielectric layer between two adjacent ones of the contact layers, in which the dielectric layer is further located between two adjacent ones of the protection layers, a material of the dielectric layer is different from a material of the protection layer.

Abstract: A bit line structure, a manufacturing method thereof, and a semiconductor memory are provided. The bit line structure includes a first bit line array and a second bit line array. The first bit line array includes a plurality of first bit lines extending in a Y direction. The plurality of first bit lines have a same length and are aligned and arranged in an X direction. The second bit line array includes a plurality of second bit lines extending in the Y direction. The plurality of second bit lines have a same length and are aligned and arranged in the X direction. The first bit line array and the second bit line array are not aligned in the X direction. The X direction is perpendicular to the Y direction.

Abstract: A signal sampling circuit and a semiconductor memory device are provided. The signal sampling circuit includes a signal input circuit, configured to determine a to-be-processed command signal and a to-be-processed chip select signal; a mode selection circuit, configured to determine a target mode clock signal and a target mode chip select signal according to the mode selection signal; a first clock processing circuit, configured to perform sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a first chip select clock signal; a second clock processing circuit, configured to perform sampling and logic operation on the to-be-processed chip select signal and the target mode chip select signal according to the target mode clock signal, to obtain a second chip select clock signal; and a command decoding circuit, configured to determine a target command signal.

Abstract: Provided are a memory and a method for manufacturing the same, and relates to the technical field of semiconductors. The manufacturing method of a memory comprises: providing a substrate; forming a plurality of sacrificial pillars arranged at intervals between each two adjacent ones of the bit line isolation walls; forming a supplementary layer on surfaces of the sacrificial pillars; performing ion implantation to the supplementary layer; etching the supplementary layer; forming insulating pillars between adjacent sacrificial pillars; removing the sacrificial pillars and the remaining supplementary layer; and forming a plurality of node contact plugs in the contact holes.

Abstract: A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.

Abstract: Embodiments of the present application provide a semiconductor structure and its manufacturing method. The method for manufacturing a semiconductor structure includes: providing a substrate and a dielectric layer located on the substrate, the substrate being provided therein with a conductive structure; etching a certain thickness of the dielectric layer to form a first groove; performing an isotropic etching process on the dielectric layer located at the bottom of the first groove to form a second groove, a maximum width of the second groove being greater than a bottom width of the first groove in a direction parallel with a surface of the substrate; and etching the dielectric layer located at the bottom of the second groove to form a third groove exposing the conductive structure.

Abstract: A fuse structure and a manufacturing method thereof are provided. The fuse structure includes: a substrate; an active region positioned above the substrate; a fuse gate structure surrounding a circumferential outer surface of the active region and electrically connected to a first power source; and a control gate structure surrounding a circumferential outer surface of the fuse gate structure and electrically connected to a second power source. A voltage of the first power source is greater than that of the second power source.