Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The manufacturing method of a semiconductor structure includes: providing a substrate having bit line contact regions; and forming a first conductive layer and a second conductive layer in each of the bit line contact regions. In the present disclosure, a first conductive layer and a second conductive layer are formed through two deposition processes separately, and a concentration of doped impurities in the first conductive layer is lower than a concentration of doped impurities in the second conductive layer.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, and Shallow Trench Isolation (STI) structures are formed in the substrate, the STI structures isolating a plurality of Active Areas (AAs) spaced in the substrate; word line trenches are formed in the substrate; an etch protection layer is formed on a surface of the first protruding structure; the STI structure is partially removed to form a second protruding structure based on the first protruding structure; the lower portion of the second protruding structure is etched to make a width of the lower portion of the second protruding structure smaller than a width of an upper portion of the second protruding structure; and a word line structure is formed in the word line trench.

Abstract: A method for manufacturing a semiconductor structure includes: forming a first diffusion film layer on a dielectric layer, a thickness of the first diffusion film layer being not less than a thickness of a doped layer; forming a hard mask on the first diffusion film layer; etching each film layer corresponding to a first region and a second region toward a substrate, until the first diffusion film layer corresponding to the first region is exposed; and next, removing a first metal oxide layer remaining on the dielectric layer corresponding to the second region. As a result of the presence of the doped layer, the hard mask corresponding to the second region has a relatively small thickness.

Abstract: A semiconductor structure and a method for manufacturing same. The semiconductor structure includes a storage unit, which includes: a first dielectric layer and a metal bit line located therein; a semiconductor channel, located on the metal bit line; a word line, disposed surrounding part of the semiconductor channel; a second dielectric layer, located between the metal bit line and the word line, and on top of the word line; a first and a second lower electrode layers, stacked on the semiconductor channel, the first lower electrode layer contacting the top surface of the semiconductor channel; an upper electrode layer, located on top of the second lower electrode layer, and surrounding the first and the second lower electrode layers; and a capacitor dielectric layer, located between the upper electrode layer and the first lower electrode layer, and between the upper electrode layer and the second lower electrode layer.

Abstract: A forming method for an opening structure includes: a substrate is provided, where a target layer is formed in the substrate, and the substrate exposes a surface of the target layer; an annular gasket is formed on the surface of the target layer, where a central through hole exposing a part of the surface of the target layer is provided in a center of the annular gasket; a dielectric layer covering the substrate, the target layer and the annular gasket is formed; and the dielectric layer is etched to form an etching hole communicating with the central through hole in the dielectric layer, where the etching hole and the central through hole form an opening structure.

Abstract: A semiconductor structure includes: a base including a substrate and a dielectric layer, herein the substrate having a front surface and a back surface that are oppositely arranged, and the dielectric layer is located on the front surface; a connecting hole penetrating the substrate and extending to the dielectric layer; a connecting structure, located in the connecting hole; and an insulating structure, located between the connecting structure and the inner wall of the connecting hole. The insulating structure, the inner wall of the connecting hole, and the connecting structure define an air gap.

Abstract: A gas circulation apparatus is applied to a pneumatic apparatus including a solenoid valve apparatus and a cylinder apparatus, and is connected in series between the solenoid valve apparatus and the cylinder apparatus. The gas circulation apparatus includes a valve core structure, a first circulation cavity, and a second circulation cavity. The valve core structure is configured to move in a first direction, so that compressed gas discharged from a first cylinder cavity of the cylinder apparatus and passing through the solenoid valve apparatus is collected and stored by the first circulation cavity, and a second cylinder cavity of the cylinder apparatus is supplied with compressed gas stored in the second circulation cavity together with the compressed gas supplied from the solenoid valve apparatus.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing a semiconductor device. Every two first wires of a first conductive layer of the semiconductor device have a common end, and every two second wires of a second conductive layer of the semiconductor device have a common end.

Abstract: Embodiments of the present disclosure relate to the field of semiconductor manufacturing, and provide a carrier device. The carrier device includes a carrier 11 and a carrying plate 12 rotatably provided on the carrier 11, where in a non-working state, the carrying plate 12 is in an inclined position; in a working state, the carrying plate 12 is in a horizontal position. The present disclosure makes it hard for impurities such as dust to accumulate on the carrier, so as to prevent a photomask from being contaminated and improve the product yield.

Abstract: A capacitance structure and a forming method thereof are provided, and the forming method includes: an annular gasket is formed on a substrate, and after a central through hole exposing a part of a surface of the substrate is formed in a center of the annular gasket, a first capacitance structure is formed in the central through hole; a dielectric layer covering the substrate, the annular gasket and the first capacitance structure is formed; the dielectric layer is etched to form an etching hole communicating with the central through hole in the dielectric layer; and a second capacitance structure connected to the first capacitance structure is formed in the etching hole.

Abstract: Embodiments of this application provide a method, an apparatus and a device for measuring a semiconductor structure. Before measurement of a to-be-measured semiconductor structure, a reference semiconductor structure corresponding to the to-be-measured semiconductor structure is set, and a first simulation model corresponding to the to-be-measured semiconductor structure and a second simulation model corresponding to the reference semiconductor structure are established, some structure parameters of the to-be-measured semiconductor structure have parameter values different from those of corresponding structure parameters of the reference semiconductor structure.

Abstract: Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor substrate; an integrated circuit region formed in the semiconductor substrate; and a seal ring arranged in the semiconductor substrate and around the integrated circuit region and configured to protect the integrated circuit region, wherein the seal ring has a wavy structure.

Abstract: A position detection and determination device and a position calibration device and method are provided. The position detection and determination device includes a standard positioning pin position limiting component configured to limit standard position information of a positioning pin of a load port of a silicon wafer pod; a positioning pin position detecting component configured to detect real-time position information of the positioning pin of the load port of the silicon wafer pod; and a determining module configured to obtain the standard position information and the real-time position information, and determine whether the position of the positioning pin of the load port of the silicon wafer pod is accurate or not according to the standard position information and the real-time position information.

Abstract: Disclosed are a data writing circuit, a data writing method, and a memory. The data writing circuit includes: a delay generation circuit, configured to generate a sub-grab signal of each storage area based on an initial grab signal and data transmission delay of each storage area, and generate a grab enable signal based on all of the sub-grab signals. A time interval between the time that each storage area receives data transmitted by a global data line and the time of receiving a column selection signal meets a preset range. A read-write control circuit writes data on a data bus into the global data line based on the grab enable signal. The global data line transmits the data to the storage area by using a column decoding circuit based on the column selection signal, so as to optimize tCCD of DRAM.

Abstract: A method for manufacturing a semiconductor structure is provided. The method for manufacturing the semiconductor structure includes: providing a substrate, in which the substrate includes a plurality of active areas separated from each other, the active areas extend along a first direction, and each active area includes a bit line contact area and two electrical connection areas located on both sides of the bit line contact area; forming first mask layers, which are separated from each other, on the substrate; forming spacer layers on two opposite side walls of each first mask layer; forming second mask layers between adjacent first mask layers; removing the spacer layers between the first mask layers and the second mask layers; and etching the substrate by using the first mask layers and the second mask layers as masks to form a bit line contact hole.

Abstract: A method for manufacturing a semiconductor structure includes: providing a substrate and a plurality of discrete bit line structures located on the substrate, the bit line structure having a metal layer therein, a top surface of the metal layer being lower than a top surface of the bit line structure; forming a first isolation film filled between the adjacent bit line structures, a top surface of the first isolation film being higher than the top surface of the metal layer and lower than the top surface of the bit line structure; forming a first dielectric film on the top and sidewalls of the bit line structure and on the top surface of the first isolation film; and etching to remove the first dielectric film on the top of the bit line structures and the top surface of the first isolation film to form a first dielectric layer, and etching to remove the first isolation film exposed by the first dielectric layer to form a first isolation layer exactly below the first dielectric layer.

Abstract: A transmission circuit includes: an upper-layer clock bonding pad configured to transmit a clock signal; M upper-layer data bonding pads configured to transmit data signals; a lower-layer clock bonding pad electrically connected with the upper-layer clock bonding pad, and an area of the lower-layer clock bonding pad is smaller than that of the upper-layer clock bonding pad; and M lower-layer data bonding pads electrically connected with the M upper-layer data bonding pads in a one-to-one correspondence, and an area of a lower-layer data bonding pad is smaller than that of an upper-layer data bonding pad. The upper-layer clock bonding pad and the upper-layer data bonding pads are located on a first layer, the lower-layer clock bonding pad and the lower-layer data bonding pads are located on a second layer.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, the base including a substrate and a first heat dissipation structure located in the substrate, heat conductivity of the first heat dissipation structure being higher than that of the substrate, the substrate including an upper surface and a lower surface opposite to each other, and a surface of the first heat dissipation structure being exposed on the upper surface of the substrate; a second heat dissipation structure, the second heat dissipation structure being at least located on an upper surface of the first heat dissipation structure; and a through silicon via (TSV) structure, the TSV structure penetrating through an entire thickness of the second heat dissipation structure and extending into the base, the second heat dissipation structure surrounding the TSV structure, and the first heat dissipation structure surrounding the TSV structure.

Abstract: A semiconductor structure and a forming method thereof are provided. The forming method of the semiconductor structure comprises: providing a substrate comprising a first area for forming a P-channel Metal Oxide Semiconductor (PMOS) transistor and a second area for forming an N-channel Metal Oxide Semiconductor (NMOS) transistor; forming a channel layer on the surface of the first area of the substrate; adjusting the oxidation rate of the channel layer to reduce the difference between the oxidation rate of the channel layer and the oxidation rate of the substrate; and oxidizing the surfaces of the channel layer and the second area of the substrate to form a first transition oxide layer covering the surface of the channel layer and a second transition oxide layer covering the surface of the second area of the substrate.

Abstract: An impedance calibration circuit, an impedance calibration method, and a memory are provided. The impedance calibration circuit includes a parameter module, an initial value generation module, and a calibration module. The parameter module is configured to perform environment detection processing and output an environment parameter signal; the initial value generation module is configured to receive the environment parameter signal, and output an initial calibration value based on the environment parameter signal when the calibration instruction signal is received; and the calibration module is configured to receive the initial calibration value, and perform impedance calibration processing based on the initial calibration value when the calibration instruction signal is received.