Patents Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC.
  • Semiconductor structure and method for preparing semiconductor structure
    Patent number: 12166028
    Abstract: A semiconductor structure and a method for preparing the semiconductor structure are provided. The semiconductor structure includes a substrate, a storage node contact and a capacitor isolating structure. The storage node contact is located on the substrate, and the capacitor isolating structure is located on the substrate, covers a side wall of the storage node contact and includes a first air gap.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Xiao Zhu
  • Method for manufacturing semiconductor device and semiconductor device
    Patent number: 12165913
    Abstract: A method for manufacturing a semiconductor device includes: forming an isolating layer on a surface of a substrate; forming a groove on the isolating layer, where the groove penetrates the isolating layer; forming a protection layer in the groove and on the isolating layer; forming a dielectric layer on the protection layer; and forming a contact hole, where the contact hole penetrates the protection layer and the dielectric layer to the surface of the substrate, respectively. The method for manufacturing the semiconductor device according to the present invention can be used not only in chemical vapor deposition but also in a process of a metal wire of a short-circuit in physical vapor deposition.
    Type: Grant
    Filed: October 3, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Suli Wang
  • Semiconductor device and oxygen removal method thereof
    Patent number: 12165883
    Abstract: The present invention discloses a semiconductor device and an oxygen removal method thereof. The semiconductor device comprises: a process cavity, an oxygen removal pipe and an oxygen detection device, wherein the oxygen detection device comprises an oxygen detection pipe, a switching ball valve and an oxygen sensor; the oxygen detection pipe comprises a first pipe, a second pipe and a third pipe which are arranged in parallel and all connected to the oxygen removal pipe and the switching ball valve; the oxygen sensor is arranged on the third pipe; and, the switching ball valve is constructed in such a way that the switching ball valve communicates the first pipe with the second pipe in an oxygen removal stage and communicates the first pipe with the third pipe in an oxygen detection stage.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Min Zuo
  • Method and apparatus for identifying probe abnormity, storage medium, and electronic device
    Patent number: 12163848
    Abstract: A method for identifying the probe abnormality includes: obtaining current temperature data of a plurality of probes, and calculating a temperature difference value between every two pieces of current temperature data; comparing the temperature difference value with a preset temperature difference, and when the temperature difference value exceeds the preset temperature difference, determining that at least one of the plurality of probes is abnormal; and heating the device to a preset temperature, and determining an abnormal probe from the plurality of probes.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Zhaoyun Dai
  • Manufacturing method for semiconductor structure
    Patent number: 12165910
    Abstract: A manufacturing method for a semiconductor structure includes: patterning and etching a semiconductor substrate to form a concave region; forming a first protective layer on a surface of the semiconductor substrate, the surface of the semiconductor substrate being a surface of a non-etched region except the concave region; forming an isolation structure in the concave region; and removing the first protective layer on the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chao Wu
  • Semiconductor transistor structure and manufacturing method
    Patent number: 12166070
    Abstract: The present application discloses a semiconductor transistor structure, which includes: a substrate formed with a well region of a first conductive type, a gate structure being disposed on the substrate; a source/drain region of a second conductive type disposed in the well region of the first conductive type, the source region and the drain region being located on two sides of the gate structure respectively; a contact hole formed at a position corresponding to the source/drain region; and a conductive metal filled in the contact hole, the bottom of the contact hole being implanted with impurity ions for decreasing the contact resistance of the contact hole, and the impurity ion concentration at a peripheral region where the bottom of the contact hole comes into contact with the source/drain region being lower than the impurity ion concentration at a middle region.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jifeng Tang
  • Interconnection structure and manufacturing method thereof and semiconductor structure
    Patent number: 12165967
    Abstract: The present disclosure provides an interconnection structure and a manufacturing method thereof and a semiconductor structure, and relates to the technical field of semiconductors. The interconnection structure includes a substrate, a dielectric layer arranged on the substrate and an insulation layer, wherein a plurality of wires are arranged in the dielectric layer at intervals; a recess is arranged in a portion, between adjacent wires, of the dielectric layer, and a bottom of the recess exposes a surface of the substrate; and the insulation layer includes an extension portion extending into the recess, and a gap is arranged between the extension portion and the substrate.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Delong Zhu
  • Semiconductor structure and a manufacturing method thereof
    Patent number: 12166133
    Abstract: A semiconductor structure includes: a substrate; a gate structure located on the substrate, wherein the gate structure comprises a first conductive layer, a barrier layer and a second conductive layer which are stacked in sequence; wherein the first conductive layer includes a first polysilicon layer, a first metal layer and a second polysilicon layer, wherein the first polysilicon layer is adjacent to the substrate and the second polysilicon layer is contiguous to the barrier layer; and wherein the first metal layer is located between the first polysilicon layer and the second polysilicon layer. The gate structure of the embodiments of the application has a straight profile and an excellent electrical performance.
    Type: Grant
    Filed: November 25, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Qiang Long
  • Mask structure, semiconductor structure and manufacturing method
    Patent number: 12167584
    Abstract: A method for manufacturing a mask structure includes: patterning a sacrificial layer and a second dielectric layer, so as to form pattern structures each including a first pattern and a second pattern, and a width of a lower portion of the pattern structures is less than a width of a upper portion of the pattern structures; forming an initial mask pattern on sidewalls of each of the plurality of pattern structures; filling a first filling layer between adjacent initial mask patterns located on the sidewalls of different pattern structures; removing the second patterns and the initial mask pattern located on sidewalls of each of the plurality of second patterns; removing the first filling layer and the first patterns, so as to form first mask patterns; and forming second mask patterns on the first mask patterns.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Jun Xia, Penghui Xu, Tao Liu, Sen Li, Kangshu Zhan
  • Method of manufacturing semiconductor structure and semiconductor structure
    Patent number: 12167589
    Abstract: The present disclosure discloses a method of manufacturing a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The method includes: providing a base, active regions arranged at intervals along a first direction being arranged in the base; forming, on the base, bit line structures arranged at intervals; forming a contact structure between two adjacent ones of the bit line structures; forming a barrier structure on the contact structure, the barrier structures being arranged in correspondence with and connected to the bit line structure, and a first recess being formed between any adjacent barrier structures; and forming a conductive structure in the first recess, the conductive structure including a protective layer and a conductive portion, and the protective layer wrapping a sidewall and a bottom wall of the conductive portion.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Guangji Li
  • Array structure of capacitors, method for manufacturing array structure of capacitors, and dynamic random access memory
    Patent number: 12167585
    Abstract: An array structure of capacitors are provided. The array structure of capacitors includes a substrate and a first connection pad, a second connection pad, a first capacitive structure and a second capacitive structure that are disposed on the substrate. The first capacitive structure is disposed outside the second capacitive structure and adjacent to an edge of the substrate. The bottom surface of the first capacitive structure towards the substrate and the top surface of the first connection pad are disposed at intervals.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Sen Li, Qiang Wan, Tao Liu, Penghui Xu
  • Method for manufacturing semiconductor structure and semiconductor structure
    Patent number: 12165879
    Abstract: A method for manufacturing a semiconductor structure and a semiconductor structure are provided. The method for manufacturing a semiconductor structure includes: forming a conductive layer, a protective layer, and a mask layer in sequence on the substrate, the mask layer including a first pattern facing the first region and a second pattern facing the second region; forming a restriction pattern located in the second region by etching the protective layer using the mask layer as a mask; and forming contact pads located in the first region and connecting wires located in the second region on the conductive layer by etching the conductive layer using the mask layer as a mask.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xinman Cao, Jun Xia, Zhongming Liu, Shijie Bai
  • Base die with error checking and correction , memory system, and semiconductor structure
    Patent number: 12164374
    Abstract: A base die is configured to receive a first data and a first encoded data in a writing phase, where the first encoded data is obtained by performing a first error correction code (ECC) encoding processing on the first data, perform a second ECC encoding processing on the first data and the first encoded data to generate a second encoded data, and transmit a second data to a memory die in the writing phase, where the second data includes the first data, the first encoded data, and the second encoded data. The base die is further configured to receive the second data from the memory die in a reading phase, perform a first error checking and correction processing, and transmit a third data in the reading phase.
    Type: Grant
    Filed: May 1, 2022
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Shu-Liang Ning
  • Semiconductor structure and forming method thereof
    Patent number: 12165874
    Abstract: A forming method of a semiconductor structure includes the following: providing a semiconductor substrate formed with a first mask layer having a preset pattern; forming a second mask layer having a first mask pattern on a surface of the first mask layer, wherein the first mask pattern includes a plurality of first sub-patterns arranged in sequence; forming a second mask pattern in the second mask layer through the first mask pattern in a self-alignment manner, wherein the second mask pattern includes the first sub-patterns of the first mask pattern and second sub-patterns corresponding to the first sub-patterns; etching the first mask layer based on the first sub-patterns and the second sub-patterns of the second mask pattern to convert the preset pattern into an active area pattern; and defining active areas in the semiconductor substrate based on the active area pattern.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jingwen Lu, Bingyu Zhu, Zhaopei Cui, Wei Feng
  • Semiconductor structure and method for manufacturing semiconductor structure
    Patent number: 12166032
    Abstract: A semiconductor structure includes a substrate, a gate dielectric layer and a conductive layer that are stacked, and the gate dielectric layer is located between the substrate and the conductive layer. The substrate includes a semiconductor substrate and an insulating substrate which are arranged on the same layer. The conductive layer includes: a gate conductor layer, a projection of which on the substrate covers the semiconductor substrate, and an external connecting layer, a projection of which on the substrate covers the insulating substrate. A groove is formed on a bottom surface, towards the substrate, of the external connecting layer and the groove is filled with an insulator.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Ching-Lun Ma
  • Method for forming ultra-shallow junction
    Patent number: 12165876
    Abstract: A method for forming an ultra-shallow junction includes the following operations: providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, providing a dopant and implanting the dopant into the epitaxial layer and a part of the semiconductor substrate, and removing the epitaxial layer, to form the ultra-shallow junction.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jian Yang
  • Layout method and layout apparatus for integrated circuit
    Patent number: 12164852
    Abstract: A layout method for an integrated circuit includes the following steps: providing a layout, the layout including a first element region and a second element region, a spacing region being provided between the first element region and the second element region; and detecting whether a width of the spacing region is less than a preset width, and if yes, marking at least one of the first element region, the second element region and the spacing region, the preset width being a minimum width meeting a requirement, wherein the requirement is to fill the spacing region with at least one dummy pattern. A layout apparatus employing the layout method for the integrated circuit can quickly and accurately position a poorly-placed element region in the layout, improve the layout efficiency and layout precision of the integrated circuit, and lay a foundation for improving photolithography quality.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: December 10, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Chuanjiang Chen, Kang Zhao, Li Bai, Li Tang, Jing Xu
  • Semiconductor structure and method for fabricating a semiconductor structure
    Patent number: 12159836
    Abstract: A semiconductor structure and a method for fabricating a semiconductor structure are provided. In the semiconductor structure, a side of a film layer structure facing away from a substrate is provided with a wiring layer, a side of the substrate facing away from the film layer structure is provided with a connecting hole extending to the wiring layer, and an insulating layer is arranged on a hole wall of the connecting hole. A barrier ring is arranged on the insulating layer, a center line of the barrier ring is arranged collinearly with a center line of the connecting hole, and diffusibility of the barrier ring is less than diffusibility of the wiring layer. A connecting post joined to the wiring layer is arranged in the connecting hole.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: December 3, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Cheng Liu
  • Semiconductor structure with shielding structure for through silicon via and manufacturing method thereof
    Patent number: 12159828
    Abstract: Provided are a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes: a through silicon via and a shielding structure disposed at an outer side of the through silicon via, in which the shielding structure includes at least two non-closed annular shielding layers surrounding the through silicon via and at least one conductive plug configured to connect two adjacent ones of the non-closed annular shielding layers; the at least two non-closed annular shielding layers and the at least one conductive plug are alternately distributed along an extending direction of the through silicon via and sequentially connected to form a conductive path, and current flow directions in two adjacent ones of the non-closed annular shielding layers in the conductive path are opposite.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 3, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Tzung-Han Lee, Chih-Cheng Liu
  • Clock circuit, memory and method for manufacturing semiconductor structure
    Patent number: 12159687
    Abstract: A clock circuit includes at least two first driving circuits and a plurality of discrete first wires located between adjacent first driving circuits, the adjacent first driving circuits are connected through at least one first wire and at least two second wires, the first driving circuits are connected with the second wires, all of the first wires connected between two second wires are connected in series with each other, the first wires are located on a first metal layer, the second wires are located on a second metal layer, and the second metal layer is above the first metal layer.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: December 3, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Meixiang Lu