Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: forming a stacked structure on the substrate, the stacked structure at least including a first material layer, a second material layer and a third material layer from bottom to top; patterning the stacked structure to obtain a first pattern structure; forming a spacer structure on a side wall of the first pattern structure, a top of the spacer structure being not lower than a top of the first material layer; and removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1.

Abstract: The present disclosure provides a method for forming semiconductor structure and a semiconductor structure. The method for forming semiconductor structure includes: providing a semiconductor base with a substrate and a first oxide material layer; wherein the first oxide material layer is arranged on the substrate, the first oxide material layer includes a first region and a second region located at edge of the first region; patterning and etching the first oxide material layer; wherein oxide line structures are formed, and an annular empty slot structure is formed; refilling a second material; wherein the second material in the first region forms a plurality of isolation line structures, and the second material in the second region forms an annular dummy isolation layer; removing the oxide line structure by patterning and etching, and forming through hole structures; and forming a conductive material layer in the through hole structures.

Abstract: A wet etching control system includes a liquid level detector, an etching agent spraying component, a cleaning agent spraying component and controller. The liquid level detector is configured to detect a liquid level of leakage liquid in a leakage liquid collection tank, and the controller is configured to control the etching agent spraying component to stop a spraying of an etching agent onto a surface of a wafer, and control the cleaning agent spraying component to spray a cleaning agent onto the surface of the wafer when the liquid level of the leakage liquid is greater than a first preset value.

Abstract: A method and apparatus for intensifying current leakage between adjacent memory cells includes that: a write operation is performed on a memory array, to form a column strip test pattern, the column strip test pattern being formed by arranging low-level memory cells and high-level memory cells in columns, and N columns of high-level memory cells being present between two adjacent columns of low-level memory cells, N?2; and voltage adjustment is performed on the low-level memory cells and the high-level memory cells, to increase potential differences between the low-level memory cells and the high-level memory cells.

Abstract: The present disclosure provides a signal line structure, a signal line driving method, and a signal line circuit. The signal line structure includes a plurality of parallel signal lines, where each of the signal lines is maintained in a drive state at any time.

Abstract: The present application relates to a method for managing and controlling a system permission, a data center, a management and control apparatus, and a storage medium. The method for managing and controlling a system permission includes: obtaining personnel change information, wherein the personnel change information includes personal information of a changed person and information about a position change mode of the changed person; obtaining a current permission interface of the changed person based on the personal information; determining, based on the permission interface, whether the changed person has an operation permission for a current object system; if the changed person has the operation permission for the current object system, determining whether the position change mode of the changed person is transfer; sending a notification message if the position change mode of the changed person is the transfer.

Abstract: Embodiments of the present application provide a weighing device that comprises a weighing unit for weighing wafers, a support structure placed on the weighing unit, at least two support platforms disposed on the support structure and each having a bearing surface for supporting peripheral regions of the wafers, and a driving part for driving the support platforms to move on the support structure, so as to adapt the at least two support platforms to bear the differently sized wafers. Since a wafer contacts merely several support platforms, cleanness of the wafer is better maintained during the weighing process; at the same time, the support platforms are enabled to stably bear differently sized wafers through adjustment of movements of the support platforms on the support structure.

Abstract: A data transmission circuit, method and memory device are provided. A comparison circuit is configured to compare global data with bus data to output a comparison result on whether the number of different bits between the global data and the bus data exceeds a preset threshold; a correction circuit is configured to check and/or correct the global data to generate corrected data; a first data conversion circuit is configured to invert the corrected data and transmit the inverted corrected data to the data bus when exceeding the preset threshold, and transmit the corrected data to the data bus when not exceeding the preset threshold, and the first data conversion circuit is further configured to output a mark signal; and a recovery circuit is configured to transmit data or inverted data on the data bus to a serial-parallel conversion circuit according to a value of the mark signal.

Abstract: The present disclosure provides a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure includes: providing a substrate, and forming discrete bit line structures on the substrate; forming a first sacrificial layer on the surface of the substrate on the bottoms of gaps of the bit line structures; forming a second sacrificial layer filling the gaps of the discrete bit line structures; patterning the second sacrificial layer and the first sacrificial layer to form openings, the formed openings and the remaining of the second sacrificial layer being arranged alternately in an extension direction of the bit line structures; forming a dielectric layer filling the openings; and, removing the remaining of the first sacrificial layer and the remaining of the second sacrificial layer to form capacitor contact holes, the formed capacitor contact holes and the dielectric layer being arranged alternately.

Abstract: A preparation method of a semiconductor structure includes: providing a base; forming several bit lines arranged in parallel and at intervals on the base, which extend in a first direction; forming capacitor contact material layers between adjacent bit lines, upper surfaces of which are lower than upper surfaces of the bit lines; forming filling medium layers on the capacitor contact material layers; forming several first mask patterns arranged in parallel and at intervals on the filling medium layers and the bit lines, which extend in a second direction that intersects with the first direction; patterning the filling medium layers based on the first mask patterns to form several grooves in the filling medium layers; forming second mask patterns in the grooves; and patterning the capacitor contact material layers based on the second mask patterns to form several cylindrical capacitor contact structures arranged in parallel and at intervals.

Abstract: A method for manufacturing a memory is provided. The method comprises: providing a substrate comprising a plurality of active areas disposed at intervals, and the active area comprising a first contact area and second contact areas; forming a plurality of bit lines disposed at intervals on the substrate; forming a first isolation layer on the bit line, the first isolation layer forming a first trench; etching the bottom of the first trench along the first trench to form a second trench exposing the second contact area; forming a first conductive layer in the first trench and the second trench; removing part of the first conductive layer to form a plurality of first through holes, so that the first conductive layer is separated into a plurality of conducting wires, and each conducting wire being connected to a second contact area; and forming a second isolation layer in the first through hole.

Abstract: The application provides a method for manufacturing a semiconductor device. The method includes the following operations. A semiconductor substrate is provided, a plurality of separate trenches being formed in the semiconductor substrate. Plasma injection is performed to form a barrier layer between adjacent trenches A respective gate structure is formed in each of the plurality of trenches. A plurality of channel regions are formed in the semiconductor substrate, each of the plurality of trenches corresponding to a respective one of the plurality of channel regions. A source/drain region is formed between each of the plurality of trenches and the barrier layer, the source/drain region being electrically connected to the respective one of the plurality of channel regions, and a conductive type of the barrier layer is opposite to a conductive type of the source/drain region.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a discharge transistor, located between the power supply pad and a ground pad, and configured to be turned on under a control of the trigger signal, so as to discharge an electrostatic charge to the ground pad; and a first controllable voltage division unit, connected to the discharge transistor, and configured to switch an operating mode under a control of a control signal. The operating mode includes a voltage division mode. When operating in the voltage division mode, the controllable voltage division unit is configured to carry a part of a voltage applied by the electrostatic charge to the discharge transistor.

Abstract: A memory and a method for forming the same are provided. In the method, a word line trench is formed in active regions and an isolation layer. The formed word line trench includes a first partial word line trench located in the active regions and a second partial word line trench located in the isolation layer. The width and depth of the second partial word line trench are greater than the width and depth of the first partial word line trench respectively. Therefore, when a word line structure is formed in the word line trench, the formed word line structure also includes a first partial word line structure located in the first partial word line trench and a second partial word line structure located in the second partial word line trench.

Abstract: An embodiment of the disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, where the substrate has a peripheral region and an array region; stacking and forming an insulating layer and a mask layer with a mask pattern on the substrate; etching the insulating layer with the mask layer as a mask to form a contact hole penetrating the insulating layer at the array region; reserving the mask layer; in a direction perpendicular to a surface of the substrate, providing a thickness difference between the mask layer of the peripheral region and the mask layer of the array region; forming a first material layer; forming a second material layer; etching a part of the mask layer with the second material layer as the mask; and removing the remaining second material layer, the remaining mask layer and the first material layer on the remaining mask layer.

Abstract: A method for manufacturing a memory device includes: a substrate is provided, the substrate including active regions; Bit Lines (BLs) are formed over the substrate, the BLs covering part of the active regions; a supporting layer is formed over the substrate covering the BLs and the substrate, first middle holes penetrating through the supporting layer and extending to the active regions are formed on the supporting layer, and gaps are formed between the first middle holes and the BLs; first protective layers are formed in the first middle holes, and etching holes which communicate with the substrate are formed in the first protective layers; the substrate and the active regions exposed in the etching holes are etched along the etching holes to form contact grooves; guide wires electrically connecting the active regions are formed in the first middle holes, the etching holes and the contact groove.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.

Abstract: A method for obtaining circuit noise parameters and an electronic device are provided. The method includes: determining a plurality of circuits to be tested, where each circuit includes one or more signal lines, and each circuit has at least one operating state; obtaining a parasitic capacitance between each signal line and all others signal lines, and determining a logic state of each signal line under each of the operating states; determining a plurality of operating state combinations for the plurality of circuits to be tested, and determining one target operating state combination from the plurality of operating state combinations; and under the target operating state combination, determining noise parameters of each one of the signal lines to be tested according to the logic state of each one of the signal lines to be tested and the parasitic capacitance.

Abstract: Embodiments relate to the field of semiconductors and provide a wordline driver circuit and a memory. The wordline driver circuit at least includes a first type of wordline drivers and a second type of wordline drivers, wherein each of the wordline drivers includes a PMOS transistor and an NMOS transistor. A first type of PMOS transistors in the first type of wordline drivers and a second type of PMOS transistors in the second type of wordline drivers are configured to receive different first control signals. The first type of PMOS transistors and the second type of PMOS transistors are arranged side by side, and the NMOS transistors included in the first type of wordline drivers and the NMOS transistors included in the second type of wordline drivers are positioned on the same side of the first type of PMOS transistors and the second type of PMOS transistors.