Abstract: A method for determining a contour of a semiconductor structure is disclosed, which includes: acquiring a best inclination angle of an electron beam; irradiating a sidewall of the semiconductor structure with the electron beam at the best inclination angle, to obtain a measured width of an orthographic projection of the sidewall of the semiconductor structure within a plane perpendicular to an incidence direction of the electron beam; and determining whether a bottom of the semiconductor structure is necked based on the measured width.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device and a semiconductor device. The method of manufacturing a semiconductor device includes: providing a substrate with trenches, and the trenches extending along a thickness direction of the substrate from a first surface of the substrate; forming a first auxiliary layer and a first conductive layer successively in the trenches, and the first conductive layer covering the first auxiliary layer; thinning the substrate on a second surface of the substrate to expose the first auxiliary layer; removing the first auxiliary layer to form first openings; forming a second medium layer on the second surface of the substrate; patterning the second medium layer to form second openings in the second medium layer, and the second openings exposing the first openings; and depositing a second initial conductive layer, the second initial conductive layer filling the first openings and the second openings.

Abstract: The present application provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing a semiconductor structure includes: forming a first conductive layer in a first trench of a substrate, where a top surface of the first conductive layer is recessed; forming a bit line structure on the first conductive layer; forming a third dielectric layer and a fourth dielectric layer, where the fourth dielectric layer at least covers the bottom and a side wall of a second trench; and removing a part of the first dielectric layer and the fourth dielectric layer that covers the bottom of the second trench, to form a third trench, where the third trench exposes the substrate. The semiconductor structure is manufactured through the method of manufacturing a semiconductor structure.

Abstract: A mixing apparatus includes: a driving device configured to drive first liquid to flow into first transfer chamber and to drive second liquid to flow into second transfer chamber, a first transfer chamber configured to store inflowed first liquid, and a second transfer chamber configured to store inflowed second liquid; a premixing chamber communicating with liquid outlet of first transfer chamber and liquid outlet of second transfer chamber; and a monitor configured to monitor volume of liquid in first transfer chamber and volume of liquid in second transfer chamber, close liquid inlet of first transfer chamber and control first liquid to flow into premixing chamber when volume of first liquid is equal to first value, and close liquid inlet of second transfer chamber and control second liquid to flow into premixing chamber when volume of second liquid is equal to second value.

Abstract: A fuse structure and a method for manufacturing the same are provided. The fuse structure includes a substrate; a fin, located on the substrate and including a first fin region; and a gate stack structure, surrounding the top and side walls of the first fin region. The gate stack structure includes a first gate stack and a second gate stack. The first gate stack covers the first fin region, the second gate stack covers the first gate stack. The first gate stack is configured to receive a first gate voltage, the second gate stack is configured to receive a second gate voltage, and the first gate voltage is greater than the second gate voltage. The fuse structure reduces the area of the fuse unit and increase the integration level of the fuse circuit.

Abstract: A semiconductor structure and a forming method thereof are disclosed in the embodiments of the present disclosure. The semiconductor structure includes: a base, wherein a gate dielectric layer defining a groove is provided in the base, a source region and a drain region are located on two opposite sides at a top of the groove, and the groove has an extension direction parallel to a surface of the base; a first gate, including a first work function layer and a first conductive layer, wherein the first work function layer covers a bottom surface and partial sidewall of the groove, and the first conductive layer covers a surface of the first work function layer; and a second gate, including a second work function layer and a second conductive layer, wherein the second gate is laminated on the first gate and has a top surface lower than the surface of the base.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors, including: a substrate, a first stacked structure is disposed on the substrate, and the first stacked structure includes a memory cell array; a plurality of word lines (WLs), where the WL is disposed in the first stacked structure and is electrically connected to the memory cell array; a plurality of bit lines (BLs), the BL is disposed beside the first stacked structure, and is electrically connected to the memory cell array; and one end of each BL away from the memory cell array forms a step, and the BL includes a first core layer and a first conductive layer covering the first core layer; and a plurality of BL plugs, each BL plug is in corresponding contact with the first conductive layer of one of the BLs.

Abstract: A method and apparatus for intensifying current leakage between adjacent memory cells includes that: a write operation is performed on a memory array, to form a column strip test pattern, the column strip test pattern being formed by arranging low-level memory cells and high-level memory cells in columns, and N columns of high-level memory cells being present between two adjacent columns of low-level memory cells, N?2; and voltage adjustment is performed on the low-level memory cells and the high-level memory cells, to increase potential differences between the low-level memory cells and the high-level memory cells.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The manufacturing method includes: forming a stacked structure on the substrate, the stacked structure at least including a first material layer, a second material layer and a third material layer from bottom to top; patterning the stacked structure to obtain a first pattern structure; forming a spacer structure on a side wall of the first pattern structure, a top of the spacer structure being not lower than a top of the first material layer; and removing the third material layer, wherein during removing the third material layer, an etching selectivity of the third material layer to the second material layer is greater than 1.

Abstract: The present disclosure provides a method for forming semiconductor structure and a semiconductor structure. The method for forming semiconductor structure includes: providing a semiconductor base with a substrate and a first oxide material layer; wherein the first oxide material layer is arranged on the substrate, the first oxide material layer includes a first region and a second region located at edge of the first region; patterning and etching the first oxide material layer; wherein oxide line structures are formed, and an annular empty slot structure is formed; refilling a second material; wherein the second material in the first region forms a plurality of isolation line structures, and the second material in the second region forms an annular dummy isolation layer; removing the oxide line structure by patterning and etching, and forming through hole structures; and forming a conductive material layer in the through hole structures.

Abstract: A wet etching control system includes a liquid level detector, an etching agent spraying component, a cleaning agent spraying component and controller. The liquid level detector is configured to detect a liquid level of leakage liquid in a leakage liquid collection tank, and the controller is configured to control the etching agent spraying component to stop a spraying of an etching agent onto a surface of a wafer, and control the cleaning agent spraying component to spray a cleaning agent onto the surface of the wafer when the liquid level of the leakage liquid is greater than a first preset value.

Abstract: The present disclosure provides a signal line structure, a signal line driving method, and a signal line circuit. The signal line structure includes a plurality of parallel signal lines, where each of the signal lines is maintained in a drive state at any time.

Abstract: Embodiments of the present application provide a weighing device that comprises a weighing unit for weighing wafers, a support structure placed on the weighing unit, at least two support platforms disposed on the support structure and each having a bearing surface for supporting peripheral regions of the wafers, and a driving part for driving the support platforms to move on the support structure, so as to adapt the at least two support platforms to bear the differently sized wafers. Since a wafer contacts merely several support platforms, cleanness of the wafer is better maintained during the weighing process; at the same time, the support platforms are enabled to stably bear differently sized wafers through adjustment of movements of the support platforms on the support structure.

Abstract: The present application relates to a method for managing and controlling a system permission, a data center, a management and control apparatus, and a storage medium. The method for managing and controlling a system permission includes: obtaining personnel change information, wherein the personnel change information includes personal information of a changed person and information about a position change mode of the changed person; obtaining a current permission interface of the changed person based on the personal information; determining, based on the permission interface, whether the changed person has an operation permission for a current object system; if the changed person has the operation permission for the current object system, determining whether the position change mode of the changed person is transfer; sending a notification message if the position change mode of the changed person is the transfer.

Abstract: A data transmission circuit, method and memory device are provided. A comparison circuit is configured to compare global data with bus data to output a comparison result on whether the number of different bits between the global data and the bus data exceeds a preset threshold; a correction circuit is configured to check and/or correct the global data to generate corrected data; a first data conversion circuit is configured to invert the corrected data and transmit the inverted corrected data to the data bus when exceeding the preset threshold, and transmit the corrected data to the data bus when not exceeding the preset threshold, and the first data conversion circuit is further configured to output a mark signal; and a recovery circuit is configured to transmit data or inverted data on the data bus to a serial-parallel conversion circuit according to a value of the mark signal.

Abstract: The present disclosure provides a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure includes: providing a substrate, and forming discrete bit line structures on the substrate; forming a first sacrificial layer on the surface of the substrate on the bottoms of gaps of the bit line structures; forming a second sacrificial layer filling the gaps of the discrete bit line structures; patterning the second sacrificial layer and the first sacrificial layer to form openings, the formed openings and the remaining of the second sacrificial layer being arranged alternately in an extension direction of the bit line structures; forming a dielectric layer filling the openings; and, removing the remaining of the first sacrificial layer and the remaining of the second sacrificial layer to form capacitor contact holes, the formed capacitor contact holes and the dielectric layer being arranged alternately.

Abstract: A memory and a method for forming the same are provided. In the method, a word line trench is formed in active regions and an isolation layer. The formed word line trench includes a first partial word line trench located in the active regions and a second partial word line trench located in the isolation layer. The width and depth of the second partial word line trench are greater than the width and depth of the first partial word line trench respectively. Therefore, when a word line structure is formed in the word line trench, the formed word line structure also includes a first partial word line structure located in the first partial word line trench and a second partial word line structure located in the second partial word line trench.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a discharge transistor, located between the power supply pad and a ground pad, and configured to be turned on under a control of the trigger signal, so as to discharge an electrostatic charge to the ground pad; and a first controllable voltage division unit, connected to the discharge transistor, and configured to switch an operating mode under a control of a control signal. The operating mode includes a voltage division mode. When operating in the voltage division mode, the controllable voltage division unit is configured to carry a part of a voltage applied by the electrostatic charge to the discharge transistor.

Abstract: A method for manufacturing a memory is provided. The method comprises: providing a substrate comprising a plurality of active areas disposed at intervals, and the active area comprising a first contact area and second contact areas; forming a plurality of bit lines disposed at intervals on the substrate; forming a first isolation layer on the bit line, the first isolation layer forming a first trench; etching the bottom of the first trench along the first trench to form a second trench exposing the second contact area; forming a first conductive layer in the first trench and the second trench; removing part of the first conductive layer to form a plurality of first through holes, so that the first conductive layer is separated into a plurality of conducting wires, and each conducting wire being connected to a second contact area; and forming a second isolation layer in the first through hole.

Abstract: The application provides a method for manufacturing a semiconductor device. The method includes the following operations. A semiconductor substrate is provided, a plurality of separate trenches being formed in the semiconductor substrate. Plasma injection is performed to form a barrier layer between adjacent trenches A respective gate structure is formed in each of the plurality of trenches. A plurality of channel regions are formed in the semiconductor substrate, each of the plurality of trenches corresponding to a respective one of the plurality of channel regions. A source/drain region is formed between each of the plurality of trenches and the barrier layer, the source/drain region being electrically connected to the respective one of the plurality of channel regions, and a conductive type of the barrier layer is opposite to a conductive type of the source/drain region.