Abstract: A memory and a method for forming the same are provided. In the method, a word line trench is formed in active regions and an isolation layer. The formed word line trench includes a first partial word line trench located in the active regions and a second partial word line trench located in the isolation layer. The width and depth of the second partial word line trench are greater than the width and depth of the first partial word line trench respectively. Therefore, when a word line structure is formed in the word line trench, the formed word line structure also includes a first partial word line structure located in the first partial word line trench and a second partial word line structure located in the second partial word line trench.

Abstract: An embodiment of the disclosure provides a method for manufacturing a semiconductor structure, including: providing a substrate, where the substrate has a peripheral region and an array region; stacking and forming an insulating layer and a mask layer with a mask pattern on the substrate; etching the insulating layer with the mask layer as a mask to form a contact hole penetrating the insulating layer at the array region; reserving the mask layer; in a direction perpendicular to a surface of the substrate, providing a thickness difference between the mask layer of the peripheral region and the mask layer of the array region; forming a first material layer; forming a second material layer; etching a part of the mask layer with the second material layer as the mask; and removing the remaining second material layer, the remaining mask layer and the first material layer on the remaining mask layer.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.

Abstract: A method for manufacturing a memory device includes: a substrate is provided, the substrate including active regions; Bit Lines (BLs) are formed over the substrate, the BLs covering part of the active regions; a supporting layer is formed over the substrate covering the BLs and the substrate, first middle holes penetrating through the supporting layer and extending to the active regions are formed on the supporting layer, and gaps are formed between the first middle holes and the BLs; first protective layers are formed in the first middle holes, and etching holes which communicate with the substrate are formed in the first protective layers; the substrate and the active regions exposed in the etching holes are etched along the etching holes to form contact grooves; guide wires electrically connecting the active regions are formed in the first middle holes, the etching holes and the contact groove.

Abstract: Embodiments relate to the field of semiconductors and provide a wordline driver circuit and a memory. The wordline driver circuit at least includes a first type of wordline drivers and a second type of wordline drivers, wherein each of the wordline drivers includes a PMOS transistor and an NMOS transistor. A first type of PMOS transistors in the first type of wordline drivers and a second type of PMOS transistors in the second type of wordline drivers are configured to receive different first control signals. The first type of PMOS transistors and the second type of PMOS transistors are arranged side by side, and the NMOS transistors included in the first type of wordline drivers and the NMOS transistors included in the second type of wordline drivers are positioned on the same side of the first type of PMOS transistors and the second type of PMOS transistors.

Abstract: A method for obtaining circuit noise parameters and an electronic device are provided. The method includes: determining a plurality of circuits to be tested, where each circuit includes one or more signal lines, and each circuit has at least one operating state; obtaining a parasitic capacitance between each signal line and all others signal lines, and determining a logic state of each signal line under each of the operating states; determining a plurality of operating state combinations for the plurality of circuits to be tested, and determining one target operating state combination from the plurality of operating state combinations; and under the target operating state combination, determining noise parameters of each one of the signal lines to be tested according to the logic state of each one of the signal lines to be tested and the parasitic capacitance.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, a gate dielectric layer and an undoped polycrystalline silicon layer sequentially stacked; performing a thermal doping process, and doping first doping ions in the polycrystalline silicon layer; and performing an ion implantation process, and doping second doping ions in a preset region of the polycrystalline silicon layer. The preset region is spaced at a preset distance from a surface of the polycrystalline silicon layer away from the gate dielectric layer in a direction perpendicular to a surface of the substrate.

Abstract: A method and device for processing wafer detection tasks, a system, and a storage medium. The method includes that: the resource manager node receives the wafer detection task from the storage server, selects the target work node from the plurality of work nodes according to weight values of the work nodes connected to the resource manager node, and allocates the wafer detection task to the target work node. The target work node selects the idle GPU from the resource pool and allocates the wafer detection task to the idle GPU for execution. The GPU preprocesses the wafer map in the wafer detection task and inputs the processed wafer map into the wafer detection model to obtain the detection result.

Abstract: Embodiments of the present application provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a substrate; a first mask layer positioned on the substrate, wherein the first mask layer has a plurality of discrete first mask patterns; and a second mask layer positioned on the first mask layer, wherein the second mask layer has a second mask pattern, and at least a part of sidewalls of the second mask pattern is positioned on tops of the first mask patterns.

Abstract: Disclosed are an active region, an active region array and a formation method thereof. The active region is formed in a substrate. The active region is provided with a wordline structure. The wordline structure penetrates the active region in a first direction and divides the active region into a source region and a drain region. The source region and the drain region are arranged in a second direction, and a size of the drain region in a third direction is greater than that of the source region in the third direction. An angle between the first direction and the second direction is an acute angle, and the third direction is perpendicular to the second direction.

Abstract: Embodiments provide a method and an apparatus for repairing a fail location. When repairing a fail location of a wafer, a fail bit in a wafer to be processed may be first determined, and a target potential fail bit associated with the fail bit may be determined based on a potential mining rule included in a mining rule library.

Abstract: Embodiments of the present application provide a semiconductor structure and its fabricating method, and a semiconductor memory. The method of fabricating a semiconductor structure comprises providing a substrate and performing ion implantation on the substrate to form an active area, forming a gate groove on surface of the substrate, measuring depth of the gate groove, and performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.

Abstract: A camera module includes a body and a cover, which are matched to form a sealed cavity; an image sensor and a micro-lens array, which are disposed in the sealed cavity; and an optical matching medium, filling the sealed cavity. The cover includes an objective lens, the center line of the image sensor is coincident with the optical axis of the objective lens, the micro-lens array is located between the image sensor and the objective lens, the optical matching medium is disposed between the objective lens and the micro-lens array, and the refractive index of the optical matching medium is greater than that of air.

Abstract: The present disclosure provides a method and an apparatus for setting wafer script, a device, and a storage medium. In response to the demand unit determining that the execution necessary condition of the script to be executed satisfies the business requirement based on the parameter information, the platform unit acquires the lot identification of the script to be executed and the corresponding production information. In response to the demand unit determining that the script to be executed is executed for the wafers corresponding to the script to be executed for the first time, the platform unit detects whether the first production information corresponding to the first wafers satisfies the execution necessary condition. If satisfied, the platform unit sets parameter information and assignment information for the first wafers, and synchronizes the first wafers with the set information to the material execution unit such that the material execution unit performs corresponding operation.

Abstract: Provided are a carrier component and a coating developer device. The carrier component includes a supporting pillar, a first carrier stage and a second carrier stage that is provided with an accommodating cavity and a through mounting hole in communication with the accommodating cavity and includes at least two casings which are assembled to form the through mounting hole matched with the supporting pillar and the accommodating cavity surrounding the first carrier stage; and the at least two casings are detachably connected to one another.

Abstract: A data transmission circuit and a data transmission method applied to the data transmission circuit are provided. The data transmission circuit includes: a data strobe module, connected to multiple memory blocks, connected to a low-bit data port through a first group of data buses, and connected to a high-bit data port through a second group of data buses, where each group of data buses include an odd data line and an even data line; and an error correction module, where each group of the data buses are provided with the error correction module, the error correction module is provided on the odd data line or the even data line, and the error correction module is configured to perform error correction on data written through the low-bit data port or the high-bit data port.

Abstract: The present application relates to a formation method for an air spacer layer and a semiconductor structure. The formation method for an air spacer layer includes: forming a first structure on a substrate and forming a second structure on the substrate, the second structure being located on a side surface of the first structure, a first trench being formed between the second structure and the first structure, and the second structure being exposed in the first trench; and growing, by an epitaxial growth process, an epitaxial layer on the second structure exposed in the first trench, the epitaxial layer not filling up the first trench, and an unfilled portion of the first trench forming the air spacer layer.

Abstract: The present disclosure provides a sample rotation system and method. The sample rotation system includes a rotation device, and the rotation device includes: a first carrier connected to a sample; a drive portion connected to the first carrier, wherein the drive portion is configured to drive the first carrier to rotate; and the first carrier drives the sample to rotate from an initial position to a target position; an acquisition device, configured to acquire a rotation state of the sample; and a control unit, electrically connected to the drive portion, and configured to control operation of the drive portion.

Abstract: A layout correction method is provided. The layout correction method includes: providing an initial layout; expanding the initial layout to obtain an expanded layout; correcting the expanded layout to obtain a corrected layout; and obtaining a target layout based on the corrected layout.

Abstract: A signal sampling circuit includes the following: a signal input circuit, configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal; a first instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to a first clock signal to obtain a first chip select clock signal; a second instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a second chip select clock signal; and an instruction decoding circuit, configured to perform decoding and sampling processing on the to-be-processed instruction signal according to be to-be-processed chip select signal and one of the first chip select clock signal and the second chip select clock signal to obtain a target instruction signal.