Abstract: A method for forming a semiconductor structure includes: providing a substrate, a gate dielectric layer and an undoped polycrystalline silicon layer sequentially stacked; performing a thermal doping process, and doping first doping ions in the polycrystalline silicon layer; and performing an ion implantation process, and doping second doping ions in a preset region of the polycrystalline silicon layer. The preset region is spaced at a preset distance from a surface of the polycrystalline silicon layer away from the gate dielectric layer in a direction perpendicular to a surface of the substrate.

Abstract: A method and device for processing wafer detection tasks, a system, and a storage medium. The method includes that: the resource manager node receives the wafer detection task from the storage server, selects the target work node from the plurality of work nodes according to weight values of the work nodes connected to the resource manager node, and allocates the wafer detection task to the target work node. The target work node selects the idle GPU from the resource pool and allocates the wafer detection task to the idle GPU for execution. The GPU preprocesses the wafer map in the wafer detection task and inputs the processed wafer map into the wafer detection model to obtain the detection result.

Abstract: Embodiments of the present application provide a semiconductor structure and a fabrication method thereof. The semiconductor structure includes a substrate; a first mask layer positioned on the substrate, wherein the first mask layer has a plurality of discrete first mask patterns; and a second mask layer positioned on the first mask layer, wherein the second mask layer has a second mask pattern, and at least a part of sidewalls of the second mask pattern is positioned on tops of the first mask patterns.

Abstract: Disclosed are an active region, an active region array and a formation method thereof. The active region is formed in a substrate. The active region is provided with a wordline structure. The wordline structure penetrates the active region in a first direction and divides the active region into a source region and a drain region. The source region and the drain region are arranged in a second direction, and a size of the drain region in a third direction is greater than that of the source region in the third direction. An angle between the first direction and the second direction is an acute angle, and the third direction is perpendicular to the second direction.

Abstract: Embodiments provide a method and an apparatus for repairing a fail location. When repairing a fail location of a wafer, a fail bit in a wafer to be processed may be first determined, and a target potential fail bit associated with the fail bit may be determined based on a potential mining rule included in a mining rule library.

Abstract: Embodiments of the present application provide a semiconductor structure and its fabricating method, and a semiconductor memory. The method of fabricating a semiconductor structure comprises providing a substrate and performing ion implantation on the substrate to form an active area, forming a gate groove on surface of the substrate, measuring depth of the gate groove, and performing ion implantation compensation, if the depth of the gate groove meets a preset condition, on the substrate according to the depth of the gate groove, and forming an ion compensation region in the active area at one side of the gate groove.

Abstract: A camera module includes a body and a cover, which are matched to form a sealed cavity; an image sensor and a micro-lens array, which are disposed in the sealed cavity; and an optical matching medium, filling the sealed cavity. The cover includes an objective lens, the center line of the image sensor is coincident with the optical axis of the objective lens, the micro-lens array is located between the image sensor and the objective lens, the optical matching medium is disposed between the objective lens and the micro-lens array, and the refractive index of the optical matching medium is greater than that of air.

Abstract: The present disclosure provides a method and an apparatus for setting wafer script, a device, and a storage medium. In response to the demand unit determining that the execution necessary condition of the script to be executed satisfies the business requirement based on the parameter information, the platform unit acquires the lot identification of the script to be executed and the corresponding production information. In response to the demand unit determining that the script to be executed is executed for the wafers corresponding to the script to be executed for the first time, the platform unit detects whether the first production information corresponding to the first wafers satisfies the execution necessary condition. If satisfied, the platform unit sets parameter information and assignment information for the first wafers, and synchronizes the first wafers with the set information to the material execution unit such that the material execution unit performs corresponding operation.

Abstract: Provided are a carrier component and a coating developer device. The carrier component includes a supporting pillar, a first carrier stage and a second carrier stage that is provided with an accommodating cavity and a through mounting hole in communication with the accommodating cavity and includes at least two casings which are assembled to form the through mounting hole matched with the supporting pillar and the accommodating cavity surrounding the first carrier stage; and the at least two casings are detachably connected to one another.

Abstract: A data transmission circuit and a data transmission method applied to the data transmission circuit are provided. The data transmission circuit includes: a data strobe module, connected to multiple memory blocks, connected to a low-bit data port through a first group of data buses, and connected to a high-bit data port through a second group of data buses, where each group of data buses include an odd data line and an even data line; and an error correction module, where each group of the data buses are provided with the error correction module, the error correction module is provided on the odd data line or the even data line, and the error correction module is configured to perform error correction on data written through the low-bit data port or the high-bit data port.

Abstract: The present application relates to a formation method for an air spacer layer and a semiconductor structure. The formation method for an air spacer layer includes: forming a first structure on a substrate and forming a second structure on the substrate, the second structure being located on a side surface of the first structure, a first trench being formed between the second structure and the first structure, and the second structure being exposed in the first trench; and growing, by an epitaxial growth process, an epitaxial layer on the second structure exposed in the first trench, the epitaxial layer not filling up the first trench, and an unfilled portion of the first trench forming the air spacer layer.

Abstract: The present disclosure provides a sample rotation system and method. The sample rotation system includes a rotation device, and the rotation device includes: a first carrier connected to a sample; a drive portion connected to the first carrier, wherein the drive portion is configured to drive the first carrier to rotate; and the first carrier drives the sample to rotate from an initial position to a target position; an acquisition device, configured to acquire a rotation state of the sample; and a control unit, electrically connected to the drive portion, and configured to control operation of the drive portion.

Abstract: A layout correction method is provided. The layout correction method includes: providing an initial layout; expanding the initial layout to obtain an expanded layout; correcting the expanded layout to obtain a corrected layout; and obtaining a target layout based on the corrected layout.

Abstract: A signal sampling circuit includes the following: a signal input circuit, configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal; a first instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to a first clock signal to obtain a first chip select clock signal; a second instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a second chip select clock signal; and an instruction decoding circuit, configured to perform decoding and sampling processing on the to-be-processed instruction signal according to be to-be-processed chip select signal and one of the first chip select clock signal and the second chip select clock signal to obtain a target instruction signal.

Abstract: An anti-fuse readout circuit, an anti-fuse memory, and a testing method are provided. The anti-fuse readout circuit includes: a latch circuit configured to latch data read out from an anti-fuse storage array; and a transmission circuit connected to an output terminal of the latch circuit, the transmission circuit being configured to transmit data latched in the latch circuit to a data port in response to a read test command.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate, the substrate includes active regions and isolation regions, each of the isolation regions includes a first trench and an isolation layer formed in the first trench; removing part of the isolation layer to form first grooves; forming a first mask layer, the first mask layer covers upper surfaces of the active regions and fills the first grooves; planarizing the first mask layer, such that an upper surface of a portion of the first mask layer located above the active regions is flush with an upper surface of a portion of the first mask layer located above the isolation regions; removing part of the first mask layer, part of the isolation layer, and part of the substrate, to form second trenches and third trenches.

Abstract: A photoresist feeding device includes a cleaning member and a storage member. The cleaning member includes a first photoresist inlet and a first photoresist outlet. The storage member includes a second photoresist inlet and a second photoresist outlet. The first photoresist outlet is connected with the second photoresist inlet. An ultrasonic generator is arranged in the cleaning member, and the ultrasonic generator is configured to generate ultrasonic waves for separating bubbles of a photoresist solution in the cleaning member from the photoresist solution, and for gathering impurity particles in the photoresist solution. The storage member is configured to store the photoresist solution that has been subjected to ultrasonic treatment.

Abstract: A local amplifying circuit, a data readout method and a memory are provided. The local amplifying circuit includes: write control transistors, configured to connect a global data line to a local data line based on a write enable signal; column selection transistors, configured to connect a bit line to the local data line based on a column selection signal; a first control NMOS transistor, having a gate connected to the local data line, one of a source and a drain being connected to the global data line and the other being connected to a corresponding read control transistor; a second control NMOS transistor, having a gate connected to a complementary local data line, one of a source and a drain being connected to a complementary global data line and the other being connected to a corresponding read control transistor.

Abstract: Embodiments of the present application relate to a semiconductor structure and a formation method thereof. The semiconductor structure formation method includes the following steps: providing a base, the base including a memory region, the memory region including a substrate, a conductive layer, and a first mask layer located on the conductive layer; patterning the first mask layer to form a plurality of first dot patterns arranged in a first array; backfilling the first mask layer to form a second mask layer covering the first mask layer; patterning the second mask layer to form a plurality of second dot patterns arranged in a second array; and etching the conductive layer by using the first dot pattern and the second dot pattern together as a mask pattern to form a plurality of independent conductive dot patterns.

Abstract: A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.