Abstract: An anti-fuse readout circuit, an anti-fuse memory, and a testing method are provided. The anti-fuse readout circuit includes: a latch circuit configured to latch data read out from an anti-fuse storage array; and a transmission circuit connected to an output terminal of the latch circuit, the transmission circuit being configured to transmit data latched in the latch circuit to a data port in response to a read test command.

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate, the substrate includes active regions and isolation regions, each of the isolation regions includes a first trench and an isolation layer formed in the first trench; removing part of the isolation layer to form first grooves; forming a first mask layer, the first mask layer covers upper surfaces of the active regions and fills the first grooves; planarizing the first mask layer, such that an upper surface of a portion of the first mask layer located above the active regions is flush with an upper surface of a portion of the first mask layer located above the isolation regions; removing part of the first mask layer, part of the isolation layer, and part of the substrate, to form second trenches and third trenches.

Abstract: A photoresist feeding device includes a cleaning member and a storage member. The cleaning member includes a first photoresist inlet and a first photoresist outlet. The storage member includes a second photoresist inlet and a second photoresist outlet. The first photoresist outlet is connected with the second photoresist inlet. An ultrasonic generator is arranged in the cleaning member, and the ultrasonic generator is configured to generate ultrasonic waves for separating bubbles of a photoresist solution in the cleaning member from the photoresist solution, and for gathering impurity particles in the photoresist solution. The storage member is configured to store the photoresist solution that has been subjected to ultrasonic treatment.

Abstract: A local amplifying circuit, a data readout method and a memory are provided. The local amplifying circuit includes: write control transistors, configured to connect a global data line to a local data line based on a write enable signal; column selection transistors, configured to connect a bit line to the local data line based on a column selection signal; a first control NMOS transistor, having a gate connected to the local data line, one of a source and a drain being connected to the global data line and the other being connected to a corresponding read control transistor; a second control NMOS transistor, having a gate connected to a complementary local data line, one of a source and a drain being connected to a complementary global data line and the other being connected to a corresponding read control transistor.

Abstract: A method for manufacturing a memory and a memory is provided. The method for manufacturing a memory includes: providing a substrate; stacking an electrode support structure, a protective layer and a first mask layer in sequence on the substrate; patterning the first mask layer on an array region, and etching the protective layer, the electrode support structure and the substrate by using the patterned first mask layer as a mask, to form capacitor holes penetrating the protective layer and the electrode support structure and extending into the substrate; removing the first mask layer; and forming a first electrode layer on side walls and bottom walls of the capacitor holes, a top surface of the first electrode layer being flush with a top surface of the electrode support structure.

Abstract: A semiconductor structure includes a conductive structure. A method for preparing the conductive structure includes: forming a semiconductor conductive layer; forming a nitrile or isonitrile transition layer on the semiconductor conductive layer; and forming a metal conductive layer on the nitrile or isonitrile transition layer.

Abstract: Embodiments of the present application relate to a semiconductor structure and a formation method thereof. The semiconductor structure formation method includes the following steps: providing a base, the base including a memory region, the memory region including a substrate, a conductive layer, and a first mask layer located on the conductive layer; patterning the first mask layer to form a plurality of first dot patterns arranged in a first array; backfilling the first mask layer to form a second mask layer covering the first mask layer; patterning the second mask layer to form a plurality of second dot patterns arranged in a second array; and etching the conductive layer by using the first dot pattern and the second dot pattern together as a mask pattern to form a plurality of independent conductive dot patterns.

Abstract: The present disclosure provides a method and an apparatus of testing a circuit, and a storage medium. The method of testing a circuit includes: determining a preset circuit module in a to-be-tested circuit and a preset node in the preset circuit module; inputting a test signal to an input terminal of the to-be-tested circuit according to a preset input rule, and obtaining a signal of the preset node in the preset circuit module; and determining a status of the preset circuit module based on the obtained signal of the preset node.

Abstract: The present disclosure provides an electrostatic discharge (ESD) protection network for a chip. The chip includes a first power supply pad, a second power supply pad, and a ground pad. The ESD protection network includes: a first ESD protection circuit, located between the first power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the first power supply pad; a second ESD protection circuit, located between the second power supply pad and the ground pad, and configured to discharge an electrostatic charge when there is an ESD pulse caused by the electrostatic charge on the second power supply pad; and a third ESD protection circuit, configured to provide a discharge path for an electrostatic charge between the first power supply pad and the second power supply pad.

Abstract: A control circuit, a method for reading and writing and a memory are provided. The control circuit includes a pre-charge circuit, an amplification circuit and an equalization circuit. The pre-charge circuit is directly electrically connected to at least one of a bit line or a complementary bit line. The amplification circuit has a first node and a second node. The equalization circuit is connected between the first node and the bit line and between the second node and the complementary bit line.

Abstract: The embodiments of the present application belong to the technical field of semiconductor manufacturing, and relate to a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method includes: the substrate is provided with a plurality of active area structures and a plurality of first hole structures arranged at intervals, first bonding pad structures are formed in the first hole structures, and the first bonding pad structures are electrically connected to the active area structures; and second bonding pad structures are formed on the first bonding pad structures, and the second bonding pad structures are connected to the first bonding pad structures, and connected to a capacitor structure.

Abstract: A method for manufacturing a memory includes: providing a substrate, capacitor contact pads being formed in the substrate; forming a laminated structure on the substrate, the laminated structure including a first laminated structure formed on the substrate and a second laminated structure formed on the first laminated structure; forming first through holes in the second laminated structure; forming a protective layer on side walls of the first through holes, the protective layer in the first through holes enclosing second through holes; and etching the first laminated structure along the second through holes to form third through holes, the third through holes exposing the capacitor contact pads.

Abstract: A method for forming the semiconductor structure includes: providing a substrate, forming a sacrificial layer and an active layer on the sacrificial layer on the substrate; etching the active layer and the sacrificial layer to form active lines extending along a first direction; forming a first isolation layer that fills a spacing between the active lines; etching ends of the active lines to form openings, and exposing the sacrificial layer on side walls of the openings; removing the sacrificial layer along the openings, and forming gap between a bottom of the active lines and the substrate; and filling the gaps with a conductive material to form bit lines extending along the first direction.

Abstract: A data analysis method includes: a target yield problem stacked graph corresponding to a wafer list is obtained, and measurement data stacked graphs of the wafer list under different types of tests are obtained; graph matching is performed on the target yield problem stacked graph and each of the measurement data stacked graphs to obtain matching degree data corresponding to the target yield problem stacked graph and each of the measurement data stacked graphs; correlation data corresponding to each of the measurement data stacked graphs and the target yield problem stacked graph is calculated; and weighted calculation is performed on the matching degree data and the correlation data, and a target measurement parameter causing a target yield problem is determined according to a result of the weighted calculation.

Abstract: A vibration attenuation structure includes: a detection component covering an outer surface of a pipe and configured to detect a vibration frequency of the pipe, and an attenuation component covering the outer surface of the pipe; wherein, the pipe being configured to transmit fluid, the detection component and the attenuation component are arranged in parallel along a direction parallel to an axis of the pipe, and the attenuation component is capable of adjusting a vibration-absorbing frequency of the attenuation component according to the vibration frequency to attenuate vibration of the pipe.

Abstract: Some examples of this disclosure relate to the field of the semiconductor technology, and disclose a method for manufacturing a semiconductor structure. The method for manufacturing of the semiconductor structure includes: providing a base, wherein the base includes a metal layer and an oxide located in the metal layer or on a surface of the metal layer; and performing heat treatment on the base, wherein a reducing gas is introduced during the heat treatment, and the metal layer is converted into a metal compound layer after the heat treatment. This disclosure can improve the performance of the semiconductor structure.

Abstract: The present application provides a machine cleaning device. The machine cleaning device includes: a guide rail arranged next to a carrying platform of the machine main body, a support slidably mounted on the guide rail, a cleaning component mounted on the support, a driving device connected to the support in a transmission way, and a controller connected to the driving device; and when the cleaning component cleans the top surface of the machine main body, the controller controls the driving device to drive the support to move along the guide rail, so as to drive the cleaning component to clean the top surface of the machine main body in a direction away from the carrying platform. So that unexpected particles are reduced to fall on the carrying platform and contaminate the carrying platform during the cleaning process.

Abstract: A memory read-write circuit includes a sense amplifier and a control signal generation module. A power voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal, and a first power voltage controlled and supplied by the first control signal is greater than a second power voltage controlled and supplied by the second control signal. A control signal generation module is configured to control, in a normal read-write mode, a pulse duration for generating the first control signal to be a first duration, and control, in a refresh mode, the pulse duration for generating the first control signal to be a second duration, the second duration being less than the first duration.

Abstract: A cleaning system is integrated in an exposure machine including an immersion cover and a workbench arranged to be movable in translation below immersion cover. The cleaning system includes an image acquisition component, a cleaning component, and a controller. The image acquisition component is configured to acquire image information of a through hole of immersion cover. The cleaning component includes a cleaning pipe disposed inside workbench and having a first end extending out of a top surface of workbench, and a vacuum pump connected to a second end of cleaning pipe. The controller is configured to judge whether through hole is blocked according to image information, control workbench to be moved in translation so that first end of cleaning pipe is located directly below blocked through hole, and control vacuum pump to apply a negative pressure to blocked through hole through cleaning pipe to clean immersion cover.

Abstract: A method and device for data synchronization, a storage medium and an electronic device are provided. The method for data synchronization includes operations as follows. Synchronization configuration information for data to be synchronized is determined, and the synchronization configuration information at least includes a data identification of the data to be synchronized and a source data table identification of a source data table where the data to be synchronized is located. A source database is queried based on the source data table identification to obtain a target source data table where the data to be synchronized is located. A field identification of the data to be synchronized is determined from the target source data table based on the data identification. A target data table is constructed based on the field identification, and the data to be synchronized is synchronized into the target data table.