Abstract: The disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure. The method for manufacturing the semiconductor structure comprises: a substrate, in which a first protective structure is formed, is provided; a first dielectric layer is formed on the substrate; and a second protective structure is formed in the first dielectric layer and the substrate. A projection of the second protective structure and a projection of the first protective structure in a direction perpendicular to a surface of the substrate are at least partially overlapped, and there is a spacing between a projection of the second protective structure and a projection of the first protective structure in a direction along the surface of the substrate.

Abstract: An active region array formation method is provided, including: providing a substrate, and forming a first hard mask layer on a surface of the substrate; patterning the first hard mask layer by using a composite etching process to form an active region shielding layer in the first hard mask layer, a pattern of the active region shielding layer being matched with a pattern of a to-be-formed active region array, wherein the composite etching process includes at least two patterning processes and at least one pattern transfer process; removing the remaining first hard mask layer; and forming the active region array in the substrate through the active region shielding layer.

Abstract: A method for forming a semiconductor structure includes: providing a substrate, the substrate including an array area and a metal interconnection area located at the periphery of the array area; and forming a metal interconnection structure in the metal interconnection area, in which the metal interconnection structure includes a plurality of stacked metal wiring layers and a plurality of connecting pillars connected between each of the metal wiring layers, each of the metal wiring layer includes a plurality of metal strips distributed at intervals, the metal strips of two adjacent metal wiring layers are staggered, and two adjacent metal strips located in a same layer are respectively connected with one same metal strip directly below them through the connecting pillars.

Abstract: An electrostatic protection circuit includes: a monitoring unit, a discharge unit, and a controllable voltage dividing unit, where the monitoring unit is connected to at least one probe pad, a discharge unit and a controllable voltage dividing unit, and the monitoring unit is configured to generate a first trigger signal in response to that an electrostatic pulse is present on any probe pad; the discharge unit connected between the at least one probe pad and the ground pad, and configured to form, under control of the first trigger signal, at least one path for discharging electrostatic charges to the ground pad; and the controllable voltage dividing unit is connected to the discharge unit and is configured to share a part of voltage of the first trigger signal for the discharge unit.

Abstract: A memory includes: bit lines (BLs) extending along a first direction and word lines (WLs) extending along a second direction; a read-write control circuit and a plurality of memory modules that are arranged along the first direction, wherein each of the plurality of memory modules includes a memory array and an amplifier array that are arranged along the first direction, the memory array includes at least one memory cell, the amplifier array includes at least one amplification unit, each of the BLs is electrically connected to a first terminal of a corresponding amplification unit, and each of the WLs is electrically connected to a corresponding memory cell; a column selection circuit, wherein the column selection circuit and the read-write control circuit are located on two adjacent sides of the plurality of memory modules as a whole, respectively; m column-select lines (CSLs) extending along the first direction.

Abstract: A semiconductor structure and a method for manufacturing same. The semiconductor structure includes: a semiconductor base, including a logical device region and a memory region; a bit line located in the memory region and an electrical contact layer located in the logical device region, which are disposed in a same layer; a first semiconductor channel located on the bit line and a second semiconductor channel located on the electrical contact layer, which are disposed in a same layer; a word line and a gate disposed in a same layer; a capacitor structure, in contact with a second doped region of the first semiconductor channel; an electrical connection structure, in contact with the fourth doped region of the second semiconductor channel; and a dielectric layer, located between the bit line and the word line, and on a side of the word line away from the semiconductor base.

Abstract: A semiconductor structure, a method for forming a semiconductor structure, a stacked structure, and a wafer stacking method are provided. The semiconductor structure includes: a semiconductor substrate; a first dielectric layer on a surface of a semiconductor substrate; a top metal layer, in which the top metal layer is located in the first dielectric layer, and the top metal layer penetrates through the first dielectric layer; and a buffer layer located between the top metal layer and the first dielectric layer.

Abstract: The present disclosure discloses a sample fixation mechanism for a test with a nano-probe, an apparatus for a test with a nano-probe, and a sample test method. The sample fixation mechanism includes a base having a first assembly surface; a holder having a second assembly surface matched with the first assembly surface, wherein the holder further has a fixation surface opposite to the second assembly surface, and the fixation surface is configured to be adhered and fixed with the sample; a lock structure having a locked state and an unlocked state, wherein in the locked state, the lock structure is capable of fixing the holder relative to the base, and in the unlocked state, the holder may be removed from the base.

Abstract: A semiconductor device and a method for forming a semiconductor device are provided. The method for forming a semiconductor device includes the following steps. A substrate is provided, in which the substrate has a periphery region, a jointing region and a device region adjoined in sequence. A metal layer is formed on an upper surface of the substrate. A dielectric layer is formed above the metal layer. An opening is formed in the dielectric layer, in which the opening is located above at least one of the periphery region or the jointing region so as to expose the metal layer to form a contact window, and a height of an upper surface of the metal layer exposed to the contact window is lower than a height of an upper surface of the metal layer located in the device region.

Abstract: The present disclosure relates to a wafer processing apparatus and a wafer transfer method. The wafer processing apparatus includes: a first machine; a second machine, including a manipulator, the manipulator transfers a wafer to the machine through a connection port; the connection port is provided between the first machine and the second machine; door panels, provided on the first machine and used to close the connection port; a detector, for detecting a current position of the door panel; a driver, connected to the door panel, for driving the door panel to move to open or close the connection port; and a controller, connected to the detector, the driver and the manipulator, for controlling the door panel to move according to the current position of the door panel to open or close the connection port, and control the manipulator to transfer the wafer.

Abstract: A semiconductor structure includes: a first base having a first face, a second base having a second face and a welded structure. The first base is provided with an electrical connection column protruding from the first face. A conductive column is provided in the second base, and a first groove and a second groove are further provided at the second face. The first groove is located above the conductive column, and the second groove exposes at least part of a side surface of the conductive column. The protruding portion of the electrical connection column is located in the second groove, and part of a side surface of the electrical connection column and part of the side surface of the conductive column overlap in staggered way in a direction perpendicular to the first face or the second surface. At least part of the welded structure is filled in the first groove.

Abstract: The present invention relates to a semiconductor structure and its forming method, and a memory and its forming method. The semiconductor structure includes a substrate, a vertical transistor on the substrate, and a bit line connected to the bottom of the vertical transistor and disposed between the bottom of the vertical transistor and the substrate. The vertical transistor in such a semiconductor structure has a relatively small plane dimension.

Abstract: Disclosed are a method and system for overlay error compensation and a storage medium. The method includes that N wafer groups are provided, wherein each wafer group includes M wafers each including a present and previous layer, and N and M are positive integers greater than or equal to 2; for each wafer, a first overlay error is determined according to device structures of the present and previous layers, and a photoetching compensation value is calculated according to the first overlay error; for each wafer group, a first average compensation value is calculated according to photoetching compensation values; a second average compensation value of the N wafer groups is calculated according to first average compensation values; and in response to that the second average compensation value is within a preset range, the second average compensation value is fed to a batch control system to compensate an (N+1)th wafer group.

Abstract: Embodiments of the disclosure provide an image fitting method. The method includes: providing a chip plate and a plurality of photographing assemblies, where the chip plate is used to place a chip tray, and the photographing assemblies are used to capture images of the chip plate; acquiring a chip plate image captured by each photographing assembly, where the chip plate image is an image of the chip plate with a partial area and the chip tray placed on the chip plate; acquiring a chip tray image included in each chip plate image, where the chip tray image is an image of the chip tray with a partial area; and fitting the plurality of chip tray images to acquire a chip image, where the chip image is an image of an entire chip tray.

Abstract: A readout circuit architecture and a sense amplification circuit are provided. The readout circuit architecture includes: a readout amplification unit including a first P-type transistor and a second P-type transistor; and a first offset compensation unit including a first offset compensation transistor and a second offset compensation transistor. The first P-type transistor is arranged in a first area and the second P-type transistor is arranged in a second area. When the first area and the second area are arranged at interval in a first direction, the first offset compensation transistor and the second offset compensation transistor are arranged in a third area located between the first area and the second area. When the first area and the second area are arranged adjacently in the first direction, the first offset compensation transistor is arranged in a fourth area and the second offset compensation transistor is arranged in a fifth area.

Abstract: A method for forming a self-aligned double pattern and semiconductor structures are provided. The method for forming a self-aligned double pattern includes the following steps: providing a substrate; sequentially forming a first mask layer, a second mask layer and a third mask layer on an upper surface of the substrate, and etching downwards from an upper surface of the third mask layer in a direction perpendicular to the upper surface of the substrate until a first trench exposing an upper surface of the first mask layer is formed; removing the third mask layer, and partially removing the first mask layer, so as to deepen the first trench; forming a spacer layer on an inner wall of the first trench, and filling the first trench with a fourth mask layer; and partially removing the spacer layer to form a second trench exposing the substrate.

Abstract: A semiconductor structure includes: a core device region and an anti-fuse device region, disposed on a same substrate; a first dielectric layer, disposed on the substrate of the core device region and the anti-fuse device region, wherein the first dielectric layer has a first dielectric constant; a second dielectric layer, disposed on the first dielectric layer of the core device region; and a conductive layer, disposed on the second dielectric layer of the core device region and the first dielectric layer of the anti-fuse device region; wherein the second dielectric layer has a dielectric constant larger than the first dielectric constant.

Abstract: A method for manufacturing a memory includes: providing a substrate having a core region provided with a word line; forming a dielectric layer on the substrate, and etching the dielectric layer to form a first filling hole exposing the word line; forming a barrier layer on a hole wall of the first filling hole, where the barrier layer located in the first filling hole surrounds and forms a first intermediate hole exposing the word line; etching the word line exposed in the first intermediate hole to remove a first residue on the word line; and forming in the first intermediate hole a first wire electrically connected to the word line.

Abstract: An embodiment of the disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate, a bit line structure located on the substrate, a capacitor contact hole located on two opposite sides of the bit line structure, and an isolation sidewall. The isolation sidewall is located between the bit line structure and the capacitor contact hole. A gap is provided between the isolation sidewalls located on the two opposite sides of the bit line structure. The gap is located on the bit line structure.

Abstract: A method for determining a contour of a semiconductor structure is disclosed, which includes: acquiring a best inclination angle of an electron beam; irradiating a sidewall of the semiconductor structure with the electron beam at the best inclination angle, to obtain a measured width of an orthographic projection of the sidewall of the semiconductor structure within a plane perpendicular to an incidence direction of the electron beam; and determining whether a bottom of the semiconductor structure is necked based on the measured width.