Abstract: A semiconductor structure includes a peripheral region and an array region. A substrate is provided. An active layer is provided in the substrate corresponding to the peripheral region. A word line groove is formed in the substrate corresponding to the array region. A word line is formed in the word line groove. The word line includes a first word line conductive layer and a second word line conductive layer with one stacked on another. A top of the first word line conductive layer is a protrusion. The protrusion protrudes along a direction pointing from the first word line conductive layer to the second word line conductive layer. An isolation layer covering the substrate is formed. A first through hole and a second through hole both penetrating through the isolation layer are formed simultaneously. The first through hole exposes the active layer. The second through hole exposes the protrusion.

Abstract: A mask pod box includes a box body and a box cover, an accommodating space is provided in the box body, an opening connecting the accommodating space and the outside is arranged on a side portion of the box body, a mask is placed into the accommodating space through the opening, the box cover is detachably installed at the side portion of the box body to close the opening.

Abstract: A semiconductor structure includes a substrate and word line structures. An isolation structure is formed in the substrate, and the isolation structure defines active areas in the substrate. The isolation structure includes a trench formed in the substrate, an isolation layer filled in the trench, and a shielding layer located in the isolation layer. The word line structures are located in the substrate, pass through the isolation structure and the active areas, and are located above the shielding layer.

Abstract: A circuit for testing a memory and a test method thereof are provided. According to the circuit for testing a memory provided by the present disclosure, a switch control circuit is connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD) and configured to input a trigger signal, so that potential of a Word Line (WL) signal end in a to-be-tested circuit meets a preset potential suspension range. Then, it is determined whether there is leakage behavior between the WL signal end and a Bit Line (BL) signal end in the to-be-tested circuit by detecting whether the present level state of a stored signal in the to-be-tested circuit is consistent with an initial level state. The to-be-tested circuit is a corresponding circuit in a single memory.

Abstract: A memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.

Abstract: An anti-fuse memory unit circuit, an array circuit and a reading and writing method are disclosed. The advantages of the device and method include: 1. the anti-fuse memory cell circuit is a pure combinational circuit, compared to time sequence circuit, after a delay of a certain time, this disclosed device closes all paths and stops the logic action of entire circuit, thus lowering the static power consumption to approximately 0; 2. this circuit constituted two positive feedback loops through the design of a switch and a logic calculation module, which enables its readout circuit to read “0” or “1” more reliably; 3. this circuit can eliminate a complicated timing sequence control part, even output the anti-fuse codes directly without latching the readout circuit output OUTA/OUTB; 4. this circuit layout is flexible.

Abstract: A Fail Bit (FB) repair method and device can be applied to repairing an FB in a chip. The method includes: a bank to be repaired including multiple target repair regions in a chip to be repaired is determined; first repair processing is performed on a first FB in each target repair region by using a redundant circuit; a second FB position determination step is executed to determine a bit position of a second FB, and second repair processing is performed on the second FB; unrepaired FBs in each target repair region is determined, and the second FB position determination step is recursively executed to obtain a test repair position of each unrepaired FB to perform third repair processing on the unrepaired FB according to the test repair position.

Abstract: A sense amplifier includes an amplification module and a control module electrically connected to the amplification module. Herein, in a case of reading a data in a memory cell on a first bit line, at an offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a first diode structure, a first current mirror structure, and a first inverter with an input terminal and an output terminal connected to each other. In a case of reading a data in a memory cell on a second bit line, at the offset compensation stage of the sense amplifier, the control module is arranged to configure the amplification module to include a second diode structure, a second current mirror structure, and a second inverter with an input terminal and an output terminal connected to each other.

Abstract: The present application provides a semiconductor structure manufacturing method and two semiconductor structures. The manufacturing method includes: providing a substrate and a silicon layer, the substrate exposing a top surface of the silicon layer; performing deposition to form an alloy layer on the silicon layer, the deposition being performed in a nitrogen-containing atmosphere, and a concentration of nitrogen atoms in the nitrogen-containing atmosphere increasing with an increase in deposition time; and annealing the alloy layer and the silicon layer. In embodiments of the present application, an increase in the concentration of nitrogen atoms can control a silicification reaction of the alloy layer, thereby preventing a line width effect and reducing the resistance of the semiconductor structure.

Abstract: The present disclosure relates to an amplifier circuit, a control method, and a memory, including: a sensing amplification circuit, including a readout node, a complementary readout node, a first node, and a second node; an isolation circuit, coupled to the readout node, the complementary readout node, a bit line, and a complementary bit line, wherein the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line at a sensing amplification stage; an offset cancellation circuit, coupled to the bit line, the complementary bit line, the readout node, and the complementary readout node, wherein the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node at an offset cancellation stage; and a processing circuit, coupled to the offset cancellation circuit.

Abstract: A data writing method and a memory, in which the data writing method is used for writing data to a memory array of the memory. The data writing method includes that: old data is read from a target column of the memory array; the old data is updated according to data to be written which carries target data bits information to generate new data; and the new data is written into the target column, in which the memory includes a plurality of data columns, the data is required to be written into the target column, and the target column includes a part of the data columns.

Abstract: A method for adjusting the memory includes: acquiring a mapping relationship between a temperature of a transistor, a gate voltage of the transistor, and an actual time at which data is written into the memory; acquiring a current temperature of the transistor; and adjusting the gate voltage, based on the current temperature and the mapping relationship, so that the actual time at which the data is written into the memory corresponding to the adjusted gate voltage is within a preset writing time.

Abstract: Provided are a control circuit and a delay circuit. The control circuit includes a control unit, a first feedback unit, and a second feedback unit. The first feedback unit outputs a first feedback signal according to a voltage of the control unit and a first reference voltage. The second feedback unit outputs a second feedback signal according to a voltage output by the first feedback unit and a second reference voltage. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the first feedback signal and adjust a voltage of a third terminal of the control unit according to the second feedback signal, to make a change value, changing along with a first parameter, of a current of the control unit be within a first range.

Abstract: Provided is a memory system, which includes: a memory, configured to, during a read or write operation, write or read multiple data, the multiple data are divided into M bytes, each having N data; and an encoding module, configured to generate, at an encoding stage, X first check codes, each based on a subset of the data at fixed bits among all the bytes, and to generate, at the encoding stage, Y second check codes based on all data in a subset of the bytes, the X first check codes are configured for at least one of error detection or error correction on the N data in each of the bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes.

Abstract: A method of manufacturing a semiconductor device comprises: forming a doped region having a first conductive type in a semiconductor substrate, and forming a gate structure on the doped region; implanting doping ions having a second conductive type to a second region of the doped region along a vertical direction, so as to form a source/drain region having the second conductive type; implanting doping ions having the first conductive type to a first region of the doped region along a tilt direction inclining toward the gate structure, and then annealing, so as to form a Halo region extending to the gate structure from the source/drain region, wherein the first region is adjacent to the gate structure and the second region is located on the side of the first region facing away from the gate structure, and the first region and the second region have no overlap region.

Abstract: A method of manufacturing a buried word line structure includes: providing a semiconductor substrate; injecting target ions into the semiconductor substrate to form an injected region in the semiconductor substrate; annealing the semiconductor substrate including the injected region to convert the injected region into an insulation region; forming a word line trench in the insulation region; and filling the word line trench with a word line metal to form a buried word line structure.

Abstract: A method for forming capacitor holes is provided. By forming a first material layer and a second material layer which are thinner and are different in materials on a supporting layer as an over-etching depth adjusting layer, when etching holes are formed in a hard mask layer and the hard mask layer is over-etched, a certain over-etching depth may be formed in the second material layer, and the etching holes terminate in the first material layer, so that the etching depth of the etching holes can be corrected and adjusted. Accordingly, the etching holes formed after the hard mask layer is over-etched can have the same depth or have a small depth difference. Therefore, time points at which the plurality of capacitors holes formed expose the corresponding connecting pads are substantially the same or differ very little, improving the performance of the DRAM.

Abstract: An on die termination (ODT) circuit includes a signal input terminal; a grounding terminal; a first transistor including a control terminal and a first terminal which are electrically connected with the signal input terminal, and a second terminal electrically connected with the grounding terminal; and a second transistor including a control terminal electrically connected with the signal input terminal, a first terminal, and a second terminal electrically connected with the grounding terminal, and when voltage of the signal input terminal changes, the first transistor has a change trend of resistance opposite to that of the second transistor.

Abstract: A method for forming an active region array and a semiconductor structure are provided. The method for forming the active region array includes the steps of: providing a substrate; forming a first mask layer on a surface of the substrate, a first etched pattern being provided in the first mask layer; forming a second mask layer covering a surface of the first mask layer; forming a third mask layer having a second etched pattern on a surface of the second mask layer; forming a flank covering a sidewall of the second etched pattern; removing the third mask layer to form a third etched pattern between adjacent flanks; etching the first mask layer along the third etched pattern to form a fourth etched pattern in the first mask layer; and etching the substrate along the first etched pattern and the fourth etched pattern, to form multiple active regions in the substrate.

Abstract: A read and write method includes: applying a read command to a memory device, the read command indicating address information; reading data to be read from a storage unit corresponding to the address information indicated by the read command; and if an error occurs in the data to be read, associating the address information indicated by the read command with a spare storage unit, and backing up the address information indicated by the read command and association information between the address information and the spare storage unit in a non-volatile storage unit based on a preset rule.