Abstract: The present disclosure discloses a method for manufacturing a capacitor, a capacitor array structure and a semiconductor memory. The method for manufacturing a capacitor includes: providing an underlayer; forming a substrate to be etched on the underlayer; enabling a wafer to include a central area and an edge area; forming a first hard mask layer having a first pattern in the central area on the substrate to be etched; using the first hard mask layer as a mask to etch the substrate to be etched, to form capacitor holes; depositing a lower electrode layer; and sequentially forming a capacitor dielectric layer and an upper electrode layer.

Abstract: Provided are an Electro Static Discharge (ESD) circuit and a memory. The ESD circuit includes: a detection circuit and multiple electrostatic discharge circuits. The detection circuit includes at least one sub-detection circuit connected between a first power end and a second power end. Each sub-detection circuit generates a sub-trigger signal based on a voltage change between the first power end and the second power end. The multiple electrostatic discharge circuits are connected between the first power end and the second power end. The multiple electrostatic discharge circuits are configured to be turned on according to the one or more sub-trigger signals.

Abstract: A capacitor structure includes two electrodes arranged oppositely and a dielectric layer located between the two electrodes, wherein the dielectric layer includes at least two perovskite layers stacked; an amorphous layer is provided between every two adjacent perovskite layers; two outermost perovskite layers of the at least two perovskite layers are in contact with the two electrodes, respectively.

Abstract: A semiconductor structure includes: a substrate; a stacked structure, contact structures, and storage nodes. The stacked structure is located on the substrate and includes semiconductor layers extending in a first direction and arranged in a spaced manner in a second direction and in a third direction, wherein the first direction and the second direction are directions parallel to a plane where the substrate is located, the first direction is perpendicular to the second direction, and the third direction is a direction perpendicular to the plane where the substrate is located. The contact structures include a first end and a second end in the first direction, wherein the first ends of the contact structures are connected to the semiconductor layers, and a material of the contact structures includes metal silicide. The storage nodes extend in the first direction and are connected to a second end of respective contact structures.

Abstract: A vibration attenuation structure includes: a detection component covering an outer surface of a pipe and configured to detect a vibration frequency of the pipe, and an attenuation component covering the outer surface of the pipe; wherein, the pipe being configured to transmit fluid, the detection component and the attenuation component are arranged in parallel along a direction parallel to an axis of the pipe, and the attenuation component is capable of adjusting a vibration-absorbing frequency of the attenuation component according to the vibration frequency to attenuate vibration of the pipe.

Abstract: A semiconductor stack structure at least includes: a substrate; connection pads located on a surface of the substrate; and a plurality of semiconductor dies located on the surface of the substrate and stacked in sequence in a first direction, the first direction being a thickness direction of the substrate. Each two adjacent semiconductor dies located in a same signal channel are connected to a same connection pad, and two semiconductor dies connected to a same connection pad are respectively located in a first channel region and a second channel region of a signal channel.

Abstract: A read/write method and a memory are provided. The read/write method includes: issuing a read command to a memory, wherein the read command points to an address; reading to-be-read data from a storage unit corresponding to the address to which the read command points; and in response to an error occurring in the to-be-read data, marking the address to which the read command points as disabled. When executing a read/write operation on the memory, the address of the storage unit is marked to distinguish an enabled storage unit from a failed storage unit in real time. A data error or a data loss can be avoided, thereby greatly improving the reliability and the service life of the memory.

Abstract: An enable control circuit and a semiconductor memory are provided. The enable control circuit includes: a counting circuit, configured to: count past clock cycles, and determine a clock cycle count value; a selection circuit, configured to determine a target clock cycle count value according to a first config signal; and a control circuit, connected to the counting circuit and the selection circuit, and configured to: control an On Die Termination (ODT) path to be in an enabled state responsive to a level state of an ODT pin signal being inverted, and start the counting circuit; and control the ODT path to switch from the enabled state to a disabled state when the clock cycle count value reaches the target clock cycle count value.

Abstract: A redundant circuit assigning method a includes: first test item is executed and first test data is acquired; a first redundant circuit assigning result including the number of assigned local redundant circuits and position data of the assigned local redundant circuits is determined according to the first test data; a second test item is executed and second test data is acquired; when fail bits acquired during execution of the second test item include one or more fail bits beyond the repair range of the assigned local redundant circuits and assigned global redundant circuits, and the assignable redundant circuits have been assigned out, target position data of fail bits in a target subdomain and a related subdomain is acquired based on the first test data and the second test data; and a second redundant circuit assigning result is determined according to the first test data and the second test data.

Abstract: A semiconductor structure manufacturing method includes: a substrate is provided, and a trench structure is formed in the substrate; a first dielectric layer is formed in the trench structure, and a top surface of the first dielectric layer is lower than a top surface of the trench structure; and a protective layer is formed in the trench structure, and the protective layers at least covers a surface of the first dielectric layer and part of a side wall of the trench structure.

Abstract: A dual reference voltage generator, an equalizer circuit, and a memory are provided. The dual reference voltage generator is configured to receive an original code, a first code and a second code, generate a first reference voltage according to the received original code and first code, and generate a second reference voltage according to the received original code and second code. The first reference voltage is different from the second reference voltage.

Abstract: Embodiments relate to a semiconductor memory and a method for writing data. The semiconductor memory includes: at least one storage array, the storage array including a plurality of data storage units and a plurality of check bit storage units; a check module, configured to receive written data and generate check data according to the written data; and a data transmission module, respectively connected to the check module and the storage array, the data transmission module being configured to transmit the written data to the plurality of data storage units and transmit the check data to the plurality of check bit storage units. A first transmission time duration of the check data is shorter than a second transmission time duration of the written data.

Abstract: The disclosure provides a method for manufacturing a semiconductor device. The method includes the following operations. A substrate on which an active region and a shallow trench isolation structure are formed, is provided. A first isolation layer is formed in the active region by an ion-doping technique. The active region surrounded by the first isolation layer is ion-implanted to form a first wordline structure. A second wordline structure is formed in the shallow trench isolation structure, and the first wordline structure and the second wordline structure are connected to form a buried wordline structure extending along a surface of the substrate.

Abstract: A method for forming a capacitor includes: providing a substrate with an electric contact portion; forming a supporting layer and a sacrificial layer which are alternately laminated on a surface of the substrate, wherein the topmost layer is a supporting layer; forming a capacitor hole penetrating through the supporting layer and the sacrificial layer and exposing the electric contact portion; forming a bottom electrode layer covering an inner surface of the capacitor hole; forming a protective layer covering a surface of the bottom electrode layer; removing the sacrificial layer, during which the bottom electrode layer being protected by the protective layer; removing the protective layer; and sequentially forming a capacitor dielectric layer and a top electrode layer.

Abstract: A clock generation circuit, a memory and a clock duty cycle calibration method are provided; the clock generation circuit comprises: an oscillation circuit, configured to generate a first oscillation signal and a second oscillation signal, a frequency of the first oscillation signal is same as a frequency of the second oscillation signal, and a phase of the first oscillation signal is opposite to a frequency of the second oscillation signal; a comparison unit, configured to receive the first oscillation signal and the second oscillation signal, and compare the duty cycle of the first oscillation signal and/or the duty cycle of the second oscillation signal; and a logical unit, connected to the comparison unit and the oscillation circuit, and configured to control the oscillation circuit according to an output result of the comparison unit, so that the duty cycle reaches a preset range.

Abstract: The embodiments of the present disclosure provide a memory and a manufacturing method of a memory. The memory includes first fins and second fins disposed on a substrate, a dielectric layer covering tops of the first fins and side wall surfaces exposed by an isolating structure, and work function layers disposed on a surface of the dielectric layer. In a direction parallel to an arrangement direction of the first fins and the second fins, the work function layers on the side walls where the adjacent first fins are opposite are provided with a first thickness, and the work function layers on the side walls where the first fins face towards the second fins are provided with a second thickness. The first thickness is greater than the second thickness.

Abstract: Embodiments relate to a method for manufacturing a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate in which a plurality of contact pads arranged in an array are provided, wherein the contact pad protrudes from the upper surface of the substrate; forming a first barrier layer on the substrate and the surface of the contact pad; forming a first conductive layer on the surface of the first barrier layer; etching the upper surface of the first conductive layer to form a first recessed structure and a second recessed structure, wherein the first recessed structure extends downward to the substrate, the projection of the first recessed structure on the substrate surrounds the contact pad, and the second recessed structure is formed in the first conductive layer and arranged above each of the corresponding contact pads.

Abstract: Embodiments provide a read operation circuit, a semiconductor memory, and a read operation method. The read operation circuit includes: a data determination module configured to read read data from the memory bank, and determine, according to the number of bits of a data change between previous read data and current read data, whether to invert the current read data to output global bus data for transmission through a global bus and inversion flag data for transmission through an inversion flag signal line; a data receiving module configured to determine whether to invert the global bus data according to the inversion flag data to output cache data; a parallel-to-serial conversion circuit configured to perform parallel-to-serial conversion on the cache data to generate output data of a DQ port; and a data buffer module configured to determine an initial state of the global bus according to enable signal and current read data.

Abstract: A method for controlling a surface glossiness of a metal workpiece includes: providing a metal workpiece; detecting the surface glossiness of the metal workpiece to obtain a first detection value; and, treating the metal workpiece by different processes according to different first detection values so that the surface glossiness of the metal workpiece satisfies the production requirements.

Abstract: An installation fixture for needle is used to install needles of an electrostatic chuck, and includes: a positioning tray, detachably disposed on an outer base of the electrostatic chuck, the positioning tray being provided with installation holes, and the installation holes corresponding to installation positions of the needles of the electrostatic chuck; and an installation fixture, detachably installed in the installation hole to adjust the installation depth of the needle.