Abstract: The present application relates to the field of semiconductor manufacturing technologies, and in particular to a method and an apparatus for automatically processing wafers. The method for automatically processing the wafers includes the following steps: providing several wafers, wherein the wafers operate on a primary path, and the primary path is a path for forming semiconductor structures on the surfaces of the wafers; determining whether there is a need for detecting defects of the wafers, and if yes, automatically switching an operating path of the wafers to a secondary path; detecting the defects of the wafers in the secondary path; and determining whether the defect detection on the wafers is finished, and if yes, automatically switching the operating path of the wafers to the primary path. The application makes it possible to automatically detect the defects of the wafers with different SWR conditions, thereby improving the automation degree of machines.

Abstract: A semiconductor device includes a substrate. A method includes the following operations. Multiple first trenches extending in a first direction are formed in the substrate. Multiple second trenches extending in a second direction are formed in the substrate in which the first trenches are formed. The first direction is perpendicular to the second direction. A first depth of a first trench is equal to a second depth of a second trench. A first insulating layer, a conducting layer and a second insulating layer are formed in sequence in the first and second trenches. The conducting layer in the first trench is separated on a cross section in the second direction to form two bit lines connected to sidewalls at either side of the first trench and extending in the first direction. Word lines extending in the second direction are formed on the conducting layer in the first and second trenches.

Abstract: A read-write circuit of a one-time programmable memory, including: an antifuse array including: n*n antifuse units, between a first node and a second node, the control terminals of switching elements in the antifuse units coupled to AND signals of different word line signals and bit line signals; the first switching device and the first capacitor connected in parallel between the second node and the second voltage source; the reference array including reference resistance and reference switching elements connected in series between the first and third nodes, the reference switching element's control end coupled to OR signals of the n*n AND signals; the second switching device and the second capacitor connected in parallel between the third node and second voltage source; a comparison circuit's first input terminal coupled to the second node and second input terminal coupled to the third node. The circuit has simpler connections, smaller area, and higher reliability.

Abstract: A comparator includes a first-stage op amp circuit, a second-stage op amp circuit, a bias circuit and a clamping circuit. The first-stage op amp circuit includes two voltage input terminals and a voltage output terminal; the second-stage op amp circuit is connected with the bias circuit and the voltage output terminal of the first-stage op amp circuit; and the clamping circuit is connected with the voltage output terminal of the first-stage op amp circuit. By adding a clamping circuit in the comparator, the highest voltage at the voltage output terminal of the first-stage op amp circuit can be clamped to a preset voltage. During the operation of the comparator, the voltage change range of the voltage output terminal of the first-stage op amp circuit is smaller, which reduces the discharge delay of the voltage output terminal of the first-stage op amp circuit, thereby increasing the flip speed of the comparator.

Abstract: A voltage generating circuit includes a first transistor and a second transistor. Voltage of a substrate of the first transistor varies with a first parameter. The first parameter is any one of a supply voltage, an operating temperature, as well as a manufacturing process of the voltage generating circuit. A gate of the first transistor is connected to a drain of the first transistor. The substrate of the first transistor serves as an output of the voltage generating circuit. A gate of the second transistor is connected to a drain of the second transistor.

Abstract: A method for manufacturing a semiconductor includes: providing a substrate; forming a polysilicon layer on the substrate, a surface, away from the substrate, of the polysilicon layer having a native oxide; and performing a nitriding treatment to the native oxide, to nitrogenize the native oxide into a silicon oxynitride layer. The native oxide is nitrogenized into the silicon oxynitride layer.

Abstract: A memory includes: bit lines (BLs) extending along a first direction and word lines (WLs) extending along a second direction; a read-write control circuit and a plurality of memory modules that are arranged along the first direction, wherein each of the plurality of memory modules includes a memory array and an amplifier array that are arranged along the first direction, the memory array includes at least one memory cell, the amplifier array includes at least one amplification unit, each of the BLs is electrically connected to a first terminal of a corresponding amplification unit, and each of the WLs is electrically connected to a corresponding memory cell; a column selection circuit, wherein the column selection circuit and the read-write control circuit are located on two adjacent sides of the plurality of memory modules as a whole, respectively; m column-select lines (CSLs) extending along the first direction.

Abstract: The present application relates to a testing method for a packaged chip, a testing system for a packaged chip, a computer device and a storage medium. The method includes following steps: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time, and subsequent testing will be performed continuously.

Abstract: A memory includes: bit lines extending along a first direction and word lines extending along a second direction; a plurality of memory modules arranged along the first direction; a column selection circuit and a read-write control driver circuit, wherein the column selection circuit and the read-write control driver circuit are located on a same side of the plurality of memory modules perpendicular to the first direction; column-select lines extending along the first direction and column connection lines extending along a third direction, wherein each of the column-select lines is electrically connected to an amplification unit arranged along the first direction and is electrically connected to the column selection circuit through the column connection line, and the column selection circuit is configured to drive the amplification unit electrically connected to the column-select line.

Abstract: A decoding drive circuit includes at least one decoding driver. The decoding driver includes a first-stage drive circuit and a second-stage drive circuit. Herein, the first-stage drive circuit is configured to receive an enabling control signal, a decoding input signal and a drive control signal, and generate a first drive signal and a second drive signal according to the enabling control signal, the drive control signal and the decoding input signal. The second-stage drive circuit is configured to generate a target word line drive signal according to the first drive signal and the second drive signal. Thus, the embodiments of the disclosure provide a new decoding drive circuit.

Abstract: A method for manufacturing a semiconductor structure includes: a substrate; and a plurality of parallel word lines and a plurality of parallel bit lines on the substrate. For each bit line, the bit line is in a zigzag shape, each two adjacent segments among segments of the bit line with the zigzag shape form a first angle, the bit line has at least one first angle, and the bit line intersects the word lines to form a second angle.

Abstract: A semiconductor structure includes a semiconductor substrate, a first isolation dam, a plurality of switching transistors and a second isolation dam. The semiconductor substrate includes a trench, an isolation region formed by a region where the trench is located, a plurality of active regions defined by the isolation region, and an electrical isolation layer, the electrical isolation layer being located on one side, away from an opening of the trench, of the trench; the first isolation dam fills the trench; the switching transistor is at least partially embedded in the active region of the semiconductor substrate; and the second isolation dam is at least partially located between the first isolation dam and the electrical isolation layer.

Abstract: A memory includes: bit lines extending along a first direction and word lines extending along a second direction; a column selection circuit and a plurality of memory modules that are arranged along the first direction; column-select lines extending along the first direction, wherein the column-select lines each are electrically connected to the column selection circuit, and the column selection circuit drives a corresponding amplification unit through one of the column-select lines; a read-write control driver circuit, wherein the read-write control driver circuit and the column selection circuit are located, respectively, on two adjacent sides of the plurality of memory modules as a whole; and a global data line extending along the second direction and an electrical connection line extending along a third direction, wherein the global data line is electrically connected to the read-write control driver circuit through the electrical connection line.

Abstract: A method for forming a contact structure includes: a base is provided and a sacrificial layer is formed on the base; the sacrificial layer is patterned to form a first gap exposing the base in the sacrificial layer; a dielectric layer is deposited in the first gap; the sacrificial layer is removed to form a second gap between dielectric layers; at least part of the dielectric layer at a periphery of the second gap is etched, to enlarge a size of an opening of the second gap.

Abstract: There are provided a semiconductor structure and a method for manufacturing the same, and a memory. The method for manufacturing a semiconductor structure includes: providing a stack structure including a first dielectric layer containing a first element; forming a first groove at least penetrating through the first dielectric layer by a first etching process, wherein after the first etching process, a first etch residue is formed in the first groove; forming a first protective layer covering a side wall, at the first dielectric layer, of the first groove; and performing a first cleaning on the stack structure formed with the first protective layer to remove the first etch residue. The first groove is configured for forming a storage cell.

Abstract: A method for forming a semiconductor structure and a method for forming a laminate structure include the following operations. A laminate structure is provided, the laminate structure including a plurality of sacrificial layers and a plurality of support layers alternately stacked on one another, each support layers includes a plurality of doped areas and a plurality of body areas. A first etching process is performed to form a plurality of first gaps penetrating through the plurality of body areas and the plurality of sacrificial layers in the laminate structure. A first material layer is deposited on inner walls of the plurality of first gaps. A second etching process is performed to remove the plurality of doped areas and the plurality of sacrificial layers to form a second gap between any two adjacent first gaps.

Abstract: A defect detecting method for a Word Line (WL) driving circuit includes: m WLs correspondingly connected to m different WL driving circuits are selected from a memory cell array and corresponding WL driving circuit arrays to serve as m WLs to be tested, one of which is set as a first WL and the remaining m-1 ones are set as second WLs; first potential is written into memory cells correspondingly connected to the m WLs to be tested; second potential is written into memory cells correspondingly connected to the first WL; real-time potentials of the memory cells connected to respective second WLs are sequentially read, and when difference value between the real-time potential of one target memory cell and the first potential is greater than first pre-set value, it is determined that the WL driving circuit connected to the second WL corresponding to the target memory cell has a defect.

Abstract: A positioning method for particles on a reticle includes: data of positions passed by a target reticle within a preset period of time is determined according to path data of the target reticle that includes particle information of the target reticle at each scan moment; position information of the target reticle when particles are present on a surface of the target reticle is determined according to the data of positions, to obtain target position data of the target reticle; reticle position data of the target reticle within adjacent scan moments is determined according to the target position data, and a particle source position of the particles on the surface of the target reticle is determined from the reticle position data according to position priorities; and a particle position analysis report of the target reticle within the preset period of time is generated according to the particle source position.

Abstract: A semiconductor structure processing method and forming method are provided. The semiconductor structure processing method includes the steps of: providing a semiconductor substrate, which is provided with feature portions having a mask layer on their top surfaces; ashing a semiconductor structure comprising the semiconductor substrate, the feature portions and the mask layer; removing the mask layer; cleaning the semiconductor structure, and forming an oxide layer on surfaces of the feature portions after the feature portions are cleaned; drying the semiconductor structure; and removing the oxide layer. During drying, one feature portion of at least one group of adjacent feature portions is inclined towards a feature portion adjacent thereto, and a distance between the inclined feature portion and the feature portion adjacent thereto after drying is smaller than a distance there between before drying.

Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.