Abstract: A method and apparatus detect a presence of a conductive relative to a capacitive sensing device, determine a velocity of the detected presence, and recognize a gesture based on the determined velocity.

Abstract: A method involves regulating an output voltage of an output transistor of a voltage regulator circuit by providing a first voltage to a front gate of the output transistor, and simultaneously with providing the first voltage to the output transistor, providing a second voltage to a back gate of the output transistor, in a manner that regulates the output voltage around a target value.

Abstract: One embodiment in accordance with the invention can include a circuit for controlling a light emitting diode (LED) lighting fixture via a power line. The circuit can include a power switch coupled to the power line and is for outputting a firing angle. Additionally, the circuit can include a control circuit coupled to the power switch and is for implementing firing angle control of the power switch. Furthermore, the circuit can include a translator coupled to receive the firing angle and for mapping the firing angle to a function of the LED lighting fixture.

Abstract: A circuit is configured to supply a first gate voltage (PG1) at a first voltage bias (VP1) to a source of a first transistor providing an output (WLS), providing the first voltage bias (VP1) to a second transistor and supplying a second voltage bias (VN1) and a second gate voltage (NG1) to a third transistor, the second transistor coupled in series to the third transistor and in parallel with the first transistor, to supply a third voltage bias (VP2) and a third gate voltage (PG2) to a fourth transistor, and a fourth voltage bias (VN2) and a fourth gate voltage (NG2) to a fifth transistor, the fourth transistor coupled in series to the fifth transistor, and the fourth and fifth transistors coupled to a gate of the second transistor, and to provide a fifth voltage bias (VN3) to a line connecting the third transistor to the fifth transistor.

Abstract: A method and apparatus to provide random access to a programmable logic register. A processing device in a programmable logic system retrieves data from a memory of the programmable logic system. The data is loaded into a configuration register configured to store configuration data for a programmable logic function over a system bus. The processing device programs a programmable logic block to implement the programmable logic function based on the configuration data, where the processing device is configured to access a first configuration register in the configuration register set, the first configuration register corresponding to a first programmable logic block in the programmable logic system, without affecting a second configuration register corresponding to a second programmable logic block.

Abstract: A touch-sensing device has a top and a bottom surface. A grounded connector is coupled to the bottom surface of the touch-sensing device and extends through the touch-sensing device to the top surface of the touch-sensing device. The touch-sensing device has a grounded layer. A first dielectric layer is on the grounded layer. A conductive layer of the touch-sensing device has an opening. The conductive layer is on the first dielectric layer. The second dielectric layer is on the conductive layer. The grounded connector is coupled to the grounded layer and extends through the opening of the conductive layer to the top surface of the second dielectric layer.

Abstract: A programmable system includes an input/output (I/O) pin that is configurable into multiple operational states. The programmable system further includes a memory device to store configuration data that, when provided to the I/O pin, causes the I/O pin to reconfigure into one of the operational states. When power is supplied to the system, the memory device is configured to provide the configuration data to the I/O pin prior to a system microcontroller becoming operational responsive to the power.

Abstract: A mutual capacitive sense array configured to improve edge performance in tracking user inputs is described. A mutual capacitive sense array comprises a first and second plurality of sense elements and a visual display configured below the sense array. The display is configured to contact the first plurality of sense elements, where each of the first and second plurality of sense elements has a first area and second area, respectively, and wherein the second area is less than the first area. A method is described to scan a mutual capacitive sense array for a user input, the array comprising a first, second, and third plurality of sense elements, wherein the third plurality of sense elements are arranged in parallel along the exterior edge of the mutual capacitive sense array. The third plurality of sense elements effectively reduces the tracking error occurring at the edges of the mutual capacitive sense array.

Abstract: Systems and methods for track-pad input are disclosed. In one embodiment, a track-pad device includes a center sensor and a plurality of radial sensors. The center sensor senses electrical characteristic change at a center of the track-pad device. The plurality of radial sensors sense electrical characteristic changes in the respective vicinity of each of the plurality of radial sensors. The plurality of radial sensors can be configured in concentric rings about the center sensor.

Abstract: A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.

Abstract: An integrated circuit device may include a first integrated circuit (IC) portion having a single memory port to access at least one memory array, the single port including a first set of address, control and data paths; and a second IC portion comprising at least a first memory port and a second memory port for providing access to the memory locations of the first IC portion through the single port of the first IC portion.

Abstract: Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer.

Abstract: A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Abstract: A semiconductor devices including non-volatile memories and methods of fabricating the same to improve performance thereof are provided. Generally, the device includes a memory transistor comprising a polysilicon channel region electrically connecting a source region and a drain region formed in a substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed above the channel region, and a high work function gate electrode formed over a surface of the ONNO stack. In one embodiment the ONNO stack includes a multi-layer charge-trapping region including an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed above the first nitride layer. Other embodiments are also disclosed.

Abstract: A method of operating a touch-sensing surface may include performing a first scan of a first set of electrodes of a touch-sensing surface, determining a presence of at least one conductive object proximate to the touch-sensing surface, in response to determining the presence of the at least one conductive object, performing a second scan of a second set of electrodes of the touch-sensing surface, and repeating the performing the second scan until the at least one conductive object is no longer proximate to the touch-sensing surface.

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.

Abstract: Disclosed is an improved substrate bias feedback circuit, and a method for operating the same.

Abstract: Embodiments described herein provide multi-panel display systems and methods for operating the same. Content is generated on a first display device based on first user input received through a user interface device coupled to the first display device. Second user input is received on the user interface device. The generated content is displayed on a second display device in response to the receiving of the second user input on the user interface device.

Abstract: An embodiment of the present invention is directed to a system including a memory interface logic unit for receiving memory access requests and corresponding information, a processor coupled to the memory interface logic, a plurality of pre-fetch buffers for handling memory accesses coupled to the memory interface logic unit, an arbiter logic unit for pre-fetching data into the plurality of pre-fetch buffers, a memory device for storing data coupled to the arbiter logic unit and the plurality of pre-fetch buffers, and busy detection logic for informing the arbiter logic unit of the current operation of the processor. The arbiter logic unit facilitates memory access via pre-fetch buffers of the processor and the memory in different or independent clock domains. The arbiter logic further allows random access without introducing additional latency.

Abstract: Sequencing circuitry for a ferroelectric RFID circuit includes an input node for receiving an external voltage, a bandgap circuit coupled to the input node, a bandgap ready circuit coupled to the bandgap circuit, a slew filter having an input coupled to the input node and to the bandgap ready circuit, a filter capacitor coupled to an output of the slew filter, and an LDO regulator having an input coupled to the output of the slew filter having a plurality of regulated voltages for use in a memory portion, a digital circuit portion, and for generating a reset signal. The sequencing circuitry further includes delay circuits for introducing a controlled delay between operational modes, POR cells for monitoring power supply voltages, and a digital state machine for monitoring internal nodes to control a shut-down pulse generator.