Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: A touch-sensor device is described. The touch sensor-device includes a panel having an array of capacitive sensors arranged to function, in a first direction, as a projected capacitance slider. The array of capacitive sensors is further arranged to function, in a second direction, as a set of independent surface capacitance sensors. A controller is coupled with the panel by an electrical component.

Abstract: An optical navigation apparatus including a package incorporating a light source and a single die of silicon. The single die of silicon includes a photodiode array configured at the detection plane to receive the speckle pattern of the scattered light from the collection optics, circuitry configured to process signals from the photodiode array to determine changes in position of the apparatus relative to the tracking surface, analog circuitry configured to control and drive current through the light source, interface circuitry configured to communicate position data by outputting the position data via a data interface, a microcontroller comprising a processor core and memory for storing computer-readable code and data, and a system bus configured to communicate instructions and data between the microcontroller and said digital, analog, and interface circuitries. Other embodiments, aspects and features are also disclosed.

Abstract: A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Abstract: Disclosed herein are a method and apparatus for extending the lifetime of a non-volatile trapped-charge memory. A method includes setting limits of a memory sense window between an intrinsic threshold voltage of a non-volatile trapped-charge memory device and one of an end-of-life (EOL) value of a threshold voltage of a programmed state of the memory device and an EOL value of a threshold voltage of an erased state of the memory device. The data state of the memory device is then sensed.

Abstract: A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Abstract: A method can include storing bank addresses, if received, on at least rising and falling edges of a same clock cycle; and if addresses stored on the rising and falling edges of the same clock cycle correspond to different banks of a memory device, starting accesses to both banks after the falling edge of the clock cycle; wherein any of the banks can be accessed in response to an address stored on a rising edge of a next clock cycle. Devices and additional methods are also disclosed.

Abstract: Apparatuses and methods of configuring a programmable analog routing system to make connections between analog functional blocks of an integrated circuit are described. A programmable analog routing system includes a first set of wires and switch sets of programmable connections coupled to a second set of wires. The programmable connections are configured to make at least one of a direct connection between two of the analog functional blocks using the second set of wires or a connection between one of the second set of wires and one of the first set of wires.

Abstract: A design tool provides interactive graphical pin assignment. In one embodiment, the design tool identifies layout restrictions of a configurable processing device that includes a plurality of pins. The design tool further provides an interactive visual representation of a pin assignment that accommodates the layout restrictions and a user input.

Abstract: A graphical user interface for tuning a programmable device comprises a first on-screen window comprising a representation of a target apparatus, wherein the target apparatus comprises the programmable device, and a second on-screen window configured to appear in response to a selection of a graphical element associated with the representation of the target apparatus, wherein the second on-screen window comprises graphical user interface (GUI) display elements representing a plurality of parameter values presently controlling operation of a device corresponding to the selected graphical element. The second on-screen window is further configured to accept a modification of at least one of the plurality of parameter values via the GUI display elements, initiate communication of the modification to the programmable device, and in response to implementing the modification in the programmable device, display operational results of the device as modified by the modification.

Abstract: An apparatus comprises a memory device to store a pre-generated Universal Serial Bus (USB) command before a USB peripheral device is coupled to a USB. The apparatus also includes a processing device to retrieve the pre-generated USB command from the memory device and transmit the pre-generated USB command to the USB peripheral device over the USB. A method comprises identifying a Universal Serial Bus (USB) peripheral device is coupled to a USB. The USB peripheral device is coupled to the universal serial bus after a pre-generated USB command is stored in a memory device. The method further includes transmitting the pre-generated USB command to the USB peripheral device over the USB in response to identifying the USB peripheral device is coupled to the USB.

Abstract: A method and apparatus perform a first scan of an input device and determine that a first signal profile received through the first scan is outside a range of a reference signal profile. The method and apparatus perform a second scan of the input device responsive to the first signal profile being outside the range of the reference signal profile and use a second signal profile received through the second scan to detect a presence of an input object at least proximate to the input device.

Abstract: A method and apparatus for scanning a first set of electrodes of a capacitive sense array using a first sensing mode to identify a presence of an object in proximity to the capacitive sense array, where scanning using the first sensing mode identifies objects not in physical contact with the capacitive sense array. The first set of electrodes is scanned using a second sensing mode to determine a location of the object in relation to the capacitive sense array, where rescanning using the second sensing mode determines locations of objects in physical contact with the capacitive sense array.

Abstract: A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

Abstract: At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.

Abstract: A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract: An embodiment of a capacitive touch screen may comprise a display device comprising a substantially transparent substrate, a first plurality of electrodes attached to the substantially transparent substrate, wherein the first plurality of electrodes are substantially parallel in a first direction, and a second plurality of electrodes, wherein each of the second plurality of electrodes is capacitively coupled with each of the first plurality of electrodes.

Abstract: Techniques for determining resistances of analog routes in electronic designs are described herein. In an example embodiment, a computer system receives first user input that indicates, in a user interface, a first component in an electronic design. The electronic design has been placed and routed for a programmable target device. The computer system receives second user input that selects, in the user interface, a particular component from one or more second components of the electronic design, where the one or more second components have analog connectivity to the first component. The computer system determines a resistance value of an analog route between the first component and the particular component, and displays the resistance value in association with the analog route in the user interface.

Abstract: A method for implementing an addressing scheme may include mapping a digital peripheral function to one or more contiguous configurable blocks in an array of configurable blocks; and assigning a memory address from a plurality of memory addresses to at least one register of each of the one or more contiguous configurable blocks based on an access mode width of the digital peripheral function and a width of each of the one or more contiguous configurable blocks.