Abstract: A capacitance measurement circuit includes a current source, a switch, and a comparator. The current source is coupled to drive a current through a circuit node. The switch is coupled to the circuit node to switch the current into a device under test (“DUT”) capacitor. The comparator includes first and second input ports. The comparator is coupled to compare a first voltage received on the first input port against a reference voltage received on the second input port. The first voltage is related to the current driven through the circuit node, a frequency at which the switch is switched, and a capacitance of the DUT capacitor.

Abstract: A semiconductor device memory device (300) can include a sense amplifier (302) enabled according to a first sense signal (setn) and a second sense signal (setp). In a sense operation, a first sense signal (setn) can be driven to a first, below ground potential. Subsequently, in the same sense operation, the first sense signal (setn) can be raised and maintained at a ground potential. Such an approach can substantially eliminate a sense amplifier stall condition that can occur under low temperature and/or low voltage operation. According to another aspect of the embodiments, a more negative logical “0” value can be written back into the memory cell during an access and/or refresh operation. This more negative value is available due to the below ground level provided during a sense operation.

Abstract: A method and apparatus for defect pixel correction in an image sensor. The method may include calculating a median of extrapolated values of right neighboring and left neighboring pixel values of a potentially defective pixel.

Abstract: A semiconductor structure, having a doped well region being formed in a substrate layer and a transistor having a terminal provided within said doped well region. The semiconductor structure also includes an oxide layer formed over the substrate layer, the doped well region, a poly silicon region, and the terminal of the transistor. The oxide layer including a step region being located where a height of the oxide layer transitions from a height associated with the doped well region to a height associated with the terminal of the transistor.

Abstract: An improved ESD protection device, integrated circuit and method for programmably altering a sensitivity of the ESD protection device is provided herein. More specifically, an active shunt ESD protection device is provided with an improved trigger circuit design. The improved trigger circuit design enables the sensitivity of the ESD protection device to be altered by providing a variety of programmable elements for adjusting an RC time constant of a slew rate detector contained therein. The programmable elements allow the RC time constant to be altered at the wafer or package level, and avoid the significant time and cost typically associated with conventional trial-and-error adjustment procedures.

Abstract: One disclosed system and method enables dynamic reconfiguration of an electronic device in association with testing activities in a convenient and efficient manner. In one implementation, the electronic device includes a bus for communicating information, a microprocessor for processing data, a programmable functional component including a plurality of functional blocks programmable to provide a plurality of functions and configurations, and a memory for storing instructions including instructions for causing the programmable functional component to change functions and configurations. The components are programmably configurable to perform a variety of functions. In one example, the memory stores a plurality of configuration images that define the configuration and functionality of the circuit. The information stored in the memory facilitates dynamic reconfiguration of the circuit in accordance with the test harness instructions.

Abstract: An apparatus that may be used to sense capacitance, as well as other functions. The apparatus includes a comparator circuit with hysteresis, a capacitor, and a current driver. The comparator circuit with hysteresis includes a first input and an output. The capacitor is coupled to the first input of the comparator circuit with hysteresis. The current driver is coupled to the output of the comparator circuit with hysteresis and to the capacitor. The current driver reciprocally sources and sinks a drive current through a terminal of the capacitor to oscillate a voltage potential at the terminal of the capacitor between a low reference potential and a high reference potential. The current driver is responsive to the output of the comparator circuit with hysteresis.

Abstract: Disclosed are various embodiments of a differential logic to CMOS logic translator including a level-shifting and buffering stage configured to receive differential inputs and to provide resulting signals with lower common mode voltage. Further, a gain stage is included to receive the resulting signals and to provide increased swing signals. A CMOS buffer is also included and is configured to receive the increased swing signals and to provide a CMOS logic output. Also disclosed is a method of translating a differential logic signal to a CMOS logic signal including level-shifting and buffering differential input signals to provide resulting signals with lower common mode voltage. The method also includes using a gain stage to provide increased swing signals from the resulting lower common mode signals and using a CMOS buffer to provide a CMOS output from the increased swing signals.

Abstract: A method and apparatus for configuring signal lines with idle codes is disclosed. According to one embodiment, data transmission system (100) may include encoders (112, 114, 116 and 118) that transmit data over signal line lanes (Lane 0 to Lane n). In an idle state, an encoder (112, 114, 116 and 118) may output one of at least two idle codes (IDLE A and IDLE B). One idle code (IDLE A) may indicate a first lane of a group of lanes. Another idle code (IDLE B) may indicate subsequent lanes of a group of lanes.

Abstract: Embodiments of the present invention relate to a programmable logical semiconductor device which is tailored for implementing digital signal processing functions. The programmable logical semiconductor device comprises one or more functional user modules and at least one of the functional user modules is configurable to implement digital signal processing functions. The programmable logical semiconductor device has analog connections that are capable of being coupled to at least one of the functional user modules and to route signals to the functional user module, including an analog signal processor coupled to the analog connection. The programmable logical semiconductor device also has one or more registers coupled to the functional user modules for storing coefficients to configure the functional user modules. One or more of the user modules comprises a switched capacitor filter.

Abstract: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of the second signal, each phase detector providing an output indicating whether the first signal is substantially aligned with the shifted copy of the second signal. A multiplexer may also be provided for receiving each of the shifted copies of the second signal, the multiplexer having a plurality of select lines coupled with the output signals of the phase detectors. Some embodiments may include a power saving mode.

Abstract: A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.

Abstract: An apparatus and method for coupling a host computer to one or more peripherals or for coupling peripherals to one another. In one example, the apparatus includes a hub having an upstream port for coupling with the host computer and one or more downstream ports for coupling with the one or more peripherals; and a local host dynamically coupled with the upstream port. In one example, when the host computer is not coupled with the upstream port, the local host communicates with the peripherals; and when the host computer is coupled with the upstream port, the local host disconnects from the upstream port so that the host computer communicates with the peripherals through the hub. In this manner, the apparatus may be used to couple peripherals to a host computer, or when a host computer is not present, the data from the peripherals may be communicated through the local host. Other embodiments are also disclosed.

Abstract: An architecture and method for cyclical redundancy check (CRC) calculation and checking is disclosed. This architecture may include a CRC calculation function, a plurality of CRC nullification functions, and a multiplexer to select the output of one of the plurality of CRC nullification functions. The architecture may further comprise N-1 CRC nullification functions, where N is number bytes in the data bus.

Abstract: The present invention is related to an image sensor comprising an array of rows (i) and columns (j) of pixels (Xij), all the pixels of one column of the array being connected to at least one common pixel output line (Ij) having at least one memory element (Mj) and at least a first amplifying element (Aj), all these amplifying elements (Aj) being connected to a common output amplifier (D). According to one preferred embodiment, said image sensor comprises: a second amplifying element (Bj) on the output of the memory element (Mj); said common output amplifier (D) having at least two input terminals; means (S1) for switching the pixel's signal on the common output line (Ij) and the memory element's signal (Mj) to respectively third and second amplifying element (Aj and Bj) of one column; and means (S2) for switching the two output signals of the amplifying elements (Aj, Bj) of one column to respectively first and second input terminals of said common output amplifier (D).

Abstract: A system and method for generating multiple current steered output signals at a centralized location and subsequently routing them to their respective output pads is shown and described. The system and method allow designers to variously stagger output pad configurations while maintaining low output-to-output skew and low jitter.

Abstract: A circuit and method for starting up a band-gap reference circuit. In one example, a startup circuit compares a Vbg voltage output of a band-gap reference circuit to a voltage (such as Vbe) across a transistor in order to selectively control whether to inject current into the band-gap reference circuit during startup.

Abstract: The present invention system and method enables dynamic reconfiguration of an electronic device with appropriate interrupts in a convenient and efficient manner. A plurality of internal peripherals, an interconnecting component and the external coupling ports are programmably configurable to perform a variety of functions with different interrupts. In response to interrupt request names that are utilized in multiple configurations, an interrupt dispatcher component directs operations to an appropriate interrupt handler for a particular configuration based upon both the configuration image and the interrupt service request indicator. The electronic device can be automatically reconfigured based upon the existence of a predetermined condition by activating different configuration images and associated interrupts are automatically included. Pending interrupt state indicators are resolved (e.g., deleted) during the reconfiguration.

Abstract: According to a data packet framing method of one embodiment, a data packet (100) may include a combination control character (102) that may convey framing information FLAG (102-0) and a code information CODE (102-1). Framing information FLAG (102-0) can indicate a start of a packet, and a code information CODE (102-1) can indicate another feature of a packet, such as size. A combination control character (102) may preferably be no larger than a data character of a data packet.

Abstract: A unity gain amplifier has a current mirror. A compensation circuit has an input coupled to an output of the current mirror. An output transistor has a base coupled to the output of the current mirror and a source of the output transistor is coupled to an output of the compensation circuit. The compensation circuit has a resistor in series with a capacitor.