Patents Assigned to Cypress Semiconductor
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Patent number: 7230856Abstract: Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer latch may further include an inverter having an input and an output. The input of the inverter is also coupled to the latch at the second node and the output of the inverter is coupled to a data output terminal. The multiplexer latch may further include a bypass circuit coupled to the latch at the first node and the data output terminal.Type: GrantFiled: October 24, 2005Date of Patent: June 12, 2007Assignee: Cypress Semiconductor CorporationInventors: Rajesh Venugopal, Greg J. Landry, Tao Peng
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Patent number: 7227212Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.Type: GrantFiled: December 23, 2004Date of Patent: June 5, 2007Assignee: Cypress Semiconductor CorporationInventors: Mira Ben-Tzur, Krishnaswamy Ramkumar, James Hunter, Thurman J. Rodgers, Mike Bruner, Klyoko Ikeuchi
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Patent number: 7227804Abstract: A memory device (200) can include a memory cell block (202), a standby current source (206), an active current source (208), and a clamping device (212). In a standby mode, a standby current source (206) can provide constant standby current ISTBY to memory cell block (202) via block supply node (204). In an active mode, active current source (208) can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit (212) can provide additional current in the event a block supply node (204) potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well (454) to source (404) back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well (454), reducing overall leakage.Type: GrantFiled: April 19, 2004Date of Patent: June 5, 2007Assignee: Cypress Semiconductor CorporationInventors: Badrinarayanan Kothandaraman, Eric Mann, Thurman J. Rodgers
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Patent number: 7225283Abstract: An arbiter circuit (100) can include a latch (106) that latches competing input signals (Req_A and Req_B) to generate latch output signals (latn1 and latn2). A filter section (108) can prevent metastable states of latch output signals (latn1 and latn2) from propagating through to output signals (Sel_A and Sel_B). If both input signals (Req_A and Req_B) are activated, a feedback circuit (110) can activate a feedback signal (fb) after a predetermined delay (?), provided both output signals (Sel_A and Sel_B) remain inactive.Type: GrantFiled: December 21, 2004Date of Patent: May 29, 2007Assignee: Cypress Semiconductor CorporationInventors: Anup Nayak, Dimitris Pantelakis, Fariborz Golshani, Derwin Mattos
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Patent number: 7224389Abstract: An active pixel comprises a sensor circuit for collecting radiation induced charges and transducing them to a measurement signal corresponding to the amount of charge collected, and a capacitor element with two nodes, where the measurement signal is present on a node of the capacitor element. The memory circuit is clocked, i.e. driven by a pulsed signal. The pulse on the memory circuit will rise the reset level at the output, which is lowered due to threshold voltage losses in the active pixel circuit, thus restoring a large signal swing. Arrays of the pixels are described, as well as a method for reading out such a pixel.Type: GrantFiled: July 16, 2001Date of Patent: May 29, 2007Assignee: Cypress Semiconductor Corporation (Belgium) BVBAInventor: Bart Dierickx
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Patent number: 7221233Abstract: According to embodiments of the invention, a nonvolatile memory such as a flash memory is used to configure a single die after packaging of the die has occurred. Thus, numerous applications may be supported by a single die or optimization within a given application may occur. According to embodiments of the invention, the nonvolatile memory may be accessed through a programming interface, and preferably, through a two-pin programming interface, to normalize parameters such as package parasitics, crystal variations, output dividers, output duty cycle, output edge rates, I/O configuration, and oscillator gain. According to an embodiment of the invention, an XO circuit configuration includes a nonvolatile memory and a stand-alone XO, where the XO circuit configuration does not require a PLL to synthesize a reference frequency produced by the XO.Type: GrantFiled: September 24, 2004Date of Patent: May 22, 2007Assignee: Cypress Semiconductor Corp.Inventors: Aaron Brennan, Mark Lugar, Mike McMenamy
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Patent number: 7221926Abstract: The present invention a method and apparatus for implementing a short range radio on a single chip. A radio, baseband, and link controller may be fully integrated within a single-chip comprising an area approximately one square centimeter. Through the integration of components upon a single package, cost and real estate savings may be provided in a baseband controller with improved performance.Type: GrantFiled: May 17, 2002Date of Patent: May 22, 2007Assignee: Cypress Semiconductor Corp.Inventor: Paul Beard
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Patent number: 7221202Abstract: A delay-locked loop (“DLL”) having reduced susceptibility to false lock. The DLL includes a delay path coupled to delay an input signal. The delay path includes two or more variable delay cells coupled in series and a feedback node coupled to an output of one of the variable delay cells. An inverter is coupled to receive the input signal and to output an inverted signal. A feedback circuit is coupled to receive the inverted signal from the inverter and to receive a feedback signal from the feedback node. The feedback circuit monitors a phase difference between the inverted signal and the feedback signal to generate a delay control signal in response to the phase difference to adjust a variable delay of the delay path.Type: GrantFiled: August 11, 2005Date of Patent: May 22, 2007Assignee: Cypress Semiconductor CorporationInventor: Ibrahim Yayla
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Patent number: 7221200Abstract: A programmable low voltage reset apparatus for a device having a plurality of power supplies comprises a low voltage signal generator for sensing when a power supply output decreases below a predetermined voltage and generating a reset signal, a reset selector for selecting one of the power supplies, and a programmable reference voltage for varying a reference voltage according to the voltage of the selected power supply.Type: GrantFiled: March 8, 2005Date of Patent: May 22, 2007Assignee: Cypress Semiconductor Corp.Inventors: Prasad Kotra, Sunil Thamaran, Shailesh Shah
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Patent number: 7221187Abstract: A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together.Type: GrantFiled: March 16, 2004Date of Patent: May 22, 2007Assignee: Cypress Semiconductor CorporationInventors: Warren Snyder, Monte Mar
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Publication number: 20070110142Abstract: A method, apparatus or system for generating a clock signal that includes determining a transmission frequency within a first frequency range for receiving or transmitting a data stream, locking a clock to the transmission frequency during a packet exchange and tuning the clock to one or more frequencies within a second frequency range after the packet exchange. The clock may be variably tuned to multiple frequencies within either the first or second range.Type: ApplicationFiled: November 16, 2005Publication date: May 17, 2007Applicant: Cypress Semiconductor CorporationInventors: Ronald Sartore, Timothy Williams
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Patent number: 7219252Abstract: According to embodiments of the invention, temperature, current, or other physical quantities associated with an integrated circuit, which can also include a processor, may be converted to a digital signal, and that digital signal used to choose a corresponding frequency offset that is added to any pre-established overclocking frequency. Embodiments of the invention allow a user to specify a dynamic range between which the frequency offset is bounded during overclocking of the integrated circuit. The programmable lower limit specifies the frequency where the integrated circuit begins to overclock. The programmable upper limit specifies the maximum overclocking frequency that is allowed. Setting the lower limit to be equal to the upper limit forces overclocking to occur at only the specified value.Type: GrantFiled: July 9, 2004Date of Patent: May 15, 2007Assignee: Cypress Semiconductor Corp.Inventors: Gabriel Li, Chwei-Po Chew, Johnson Tsai
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Patent number: 7215246Abstract: A system allows binding in a one-way wireless transmission. The system includes a transmitting wireless device having a button and a receiving wireless device having a signaling mechanism. The second wireless device receives a code transmitted from the first wireless device when the button is pressed, determines if the code has been previously received, and accepts the code if not previously received. If the code is accepted, the second wireless device signals acceptance.Type: GrantFiled: June 24, 2004Date of Patent: May 8, 2007Assignee: Cypress Semiconductor Corp.Inventors: Paul Beard, Ryan Winfield Woodings
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Patent number: 7215214Abstract: An oscillator circuit is provided having an oscillating amplifier circuit connected to a resonator. The oscillator/amplifier and resonator are preferably fabricated on a single die using semiconductor fabrication tools. Included with the circuitry is a temperature sensor or transducer, an execution unit, non-volatile memory, a modulator, and frequency synthesizer, all of which are integrated together on the substrate, along with the piezoelectric crystal resonator. The frequency synthesizer can preferably include a phase-locked loop with a divider that is in a feedback loop of the phase-locked loop, in which a divide-by value is received from a modulator that achieves finer and higher resolution frequency selectivity from the voltage-controlled oscillator, also within the phase-locked loop, as an output from the crystal oscillator.Type: GrantFiled: July 13, 2004Date of Patent: May 8, 2007Assignee: Cypress Semiconductor Corp.Inventors: Babak Taheri, Steve Whelan, Greg Richmond
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Patent number: 7215170Abstract: A low voltage logic circuit with asynchronous SET and/or RESET functions is described herein. The low voltage logic circuit may be primarily used in forming low voltage flip-flop circuits, but may also be used to form multiplexers and other logic configurations. The flip-flop circuit described herein improves upon existing low voltage architectures by providing a flip-flop circuit, which can operate at relatively low supply voltages (e.g., less than about 1.8V), with SET and/or RESET capability. In doing so, the improved flip-flop circuit may be used within a phase frequency detector, programmable counter, or frequency divider of a phase locked loop (PLL) or delay locked loop (DLL) device. However, the improved flip-flop circuit may be used with any low voltage circuit or device that may require, use or benefit from a SET or RESET function.Type: GrantFiled: September 15, 2004Date of Patent: May 8, 2007Assignee: Cypress Semiconductor Corp.Inventors: Pozeng Kang, Gabriel Ming-Yu Li
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Publication number: 20070096949Abstract: An improved key matrix scanning technique conducts a first pre-scan on a first array of connections in a key matrix to identify any activated keys or buttons associated with the first array. A second sub-scan is conducted on a second array of connections in the key matrix but only for the connections in the first array that are detected as having activated keys.Type: ApplicationFiled: December 20, 2006Publication date: May 3, 2007Applicant: CYPRESS SEMICONDUCTOR CORP.Inventors: David Wright, Ray Asbury
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Publication number: 20070098111Abstract: A transmitter digital signal processor (DSP) circuit has a transmit frequency represented by n-bit data output from a look up table (LUT). The n-bit data is outputted to an n-bit accumulator structured to overflow at a rate based on the output n-bit data to output a phase. The circuit further has device structured to add an n-bit signed constant to the accumulator to offset the frequency represented by the n-bit data output from the LUT. A transceiver on a semiconductor chip may include as part of a transmitter circuit, a transmit DSP circuit that has the LUT, accumulator and device providing an n-bit signed constant to the accumulator to offset a transmit frequency in order to allow a receiver circuit on the transceiver to communicate directly with the transmitter circuit, and thus allowing testing of the transceiver.Type: ApplicationFiled: October 27, 2005Publication date: May 3, 2007Applicant: Cypress Semiconductor CorporationInventors: Mark Gehring, Russell Moen, Brent Jensen
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Patent number: 7212076Abstract: A mixed signal method and system for tuning a voltage controlled oscillator is described. The method includes dividing a frequency range of an oscillator circuit into a plurality of regions, digitally selecting and tuning one of the plurality of regions of the divided frequency range of the oscillator circuit, and further tuning the selected region of the frequency range of the oscillator circuit via one or more analog tuning elements.Type: GrantFiled: September 17, 2004Date of Patent: May 1, 2007Assignee: Cypress Semiconductor CorpoartionInventors: Babak Taheri, Gopal Patil
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Patent number: 7206733Abstract: A multi-purpose interface between a host computer and an FPGA. This interface uses an IEEE 1284 compliant EPP mode connection. When the host computer is initialized, a reset of the FPGA is carried out to clear the configuration memory of the FPGA. The data lines of the interface are then used to communicate unidirectional configuration data into the FPGA. The data are clocked by the host computer using the data strobe signal line to clock data into the FPGA. When the FPGA has been fully programmed, including programming an IEEE 1284 compliant EPP mode interface into the FPGA, the data lines are used for bidirectional communication between the host computer and the configured FPGA, in this embodiment operating as a virtual microcontroller.Type: GrantFiled: October 10, 2001Date of Patent: April 17, 2007Assignee: Cypress Semiconductor CorporationInventor: Craig Nemecek
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Patent number: 7206247Abstract: An antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse may comprise a capacitor. Current used to program an antifuse cell is controlled using a programming current regulator. The programming current regulator may include components that form a current mirror with components of the antifuse cell to tightly control programming current through the antifuse. Dynamic current flowing through a substrate of an antifuse cell is limited using a current limiting resistor directly in series with an antifuse of the antifuse cell. The current limiting resistor minimizes or prevents excessive programming current.Type: GrantFiled: September 29, 2005Date of Patent: April 17, 2007Assignee: Cypress Semiconductor CorporationInventor: Fredrick B. Jenne
