Abstract: A unity gain amplifier has a current mirror. A compensation circuit has an input coupled to an output of the current mirror. An output transistor has a base coupled to the output of the current mirror and a source of the output transistor is coupled to an output of the compensation circuit. The compensation circuit has a resistor in series with a capacitor.

Abstract: A buffer circuit, system, and method are provided. The buffer circuit includes a control circuit coupled to an output of the buffer, or possibly to an output of the first stage of a buffer. A pre-charge circuit is also provided coupled to bias an input of the control circuit to a voltage value approximately near a threshold voltage of the control circuit. The pre-charge bias amount is slightly less than the amount needed to place the control circuit in a high current conduction state. A coupling circuit is thereafter used and adapted to couple an input voltage applied to the buffer circuit to the input of the control circuit. This causes the control circuit to enter the high current conduction state. Depending on the input impedance of the coupling circuit, by pre-charging the coupling circuit input, less time is needed to cause the coupling circuit to enter and thereafter leave a high current conduction state.

Abstract: An input circuit (200) operating at a predetermined power supply voltage (VPW) can level shift a high voltage input signal (VINHV) from a higher voltage value to the lower power supply voltage (VPW) level. An input circuit (200) can include input transistors (206-0 and 206-1) having a source-follower configuration. A first input transistor (206-0) receives a high voltage input signal (VINHV) and a second input transistor (206-1) receives a reference voltage (VREF), which can both reach levels greater than power supply voltage (VPW). A compare circuit (204) can reduce duty cycle distortion to generate a lower voltage input signal (VINLV). Input circuit (200) can provide level shifting from LVTTL levels to low voltage CMOS levels without the need for multiple power supply voltages.

Abstract: An antifuse cell includes a select transistor, a blocking transistor, and an antifuse. The select transistor allows for selection of the antifuse cell among an array of antifuse cells, while the blocking transistor limits the amount of voltage that may be directly applied to the select transistor. The antifuse including a capacitor. The capacitor may include a gate over a gate oxide and an n-well under the gate oxide. The n-well may have two n+ regions used as contact points for the n-well. Upon programming, an electrically conductive path (e.g., a short) is permanently burned through the gate oxide. The antifuse cell occupies a relatively small area while providing a relatively tight read current distribution.

Abstract: System and method for a multi-layer antenna is shown and described. A multi-layer antenna includes a plurality of antenna layers that are stacked and aligned to minimize an antenna footprint without degrading electrical performance. This reduced antenna footprint allows system designer the ability to reduce the overall size of wireless communication devices incorporating the multi-layer antenna.

Abstract: A bus architecture includes master devices that are each capable of initiating a data transfer procedure by generating a bus request signal. Each of the master devices is arranged to transmit an address signal to an address input of a multiplexer, to transmit a data signal to a data input of the multiplexer, and to transmit a control signal to a control input of the multiplexer. The control signals may include burst type control signals. The multiplexer is capable of selectively coupling a selected master device chosen from the group consisting of the master devices to a bus. The bus architecture further includes an arbiter arranged to receive the bus request signals as first inputs and arranged to receive the burst type control signals as second inputs, where the burst type control signals are received from an ingress side of the multiplexer.

Abstract: A circuit for shifting a signal from a first voltage level to a second voltage level. In one embodiment, a voltage translator circuit has first and second transistors that are cross-coupled; a third transistor having a gate coupled with the input signal, the third transistor being coupled between the gate of the second cross-coupled transistor and the drain of the first cross-coupled transistor; and a fourth transistor having a gate coupled with an inverted version of the input signal, the fourth transistor being coupled between the gate of the first cross-coupled transistor and the drain of the second cross-coupled transistor. In another embodiment, the circuit may have, as part of its output stage, a first and second output transistors connected in series, and a third output transistor coupled between the second output transistor and ground, the third output transistor having a gate coupled with a high voltage supply.

Abstract: A convenient, low-cost method is provided herein for switching between one or more source devices, which are connected to a sink device via a multimedia interface. According to one embodiment, the method described herein may be used for switching between a plurality of source devices compatible with the High Definition Multimedia Interface (HDMI™) or any other similar audio/video interfaces. In some cases, the method may utilize priority data to connect the source device having the highest priority to the sink. In other cases, the method may allow manual/remote selection to override an original source selection based on priority.

Abstract: This invention provides a method for improved frequency agility and preferably includes transmitting and receiving data on a primary channel; finding a secondary channel substantially free from interference during a period between data transmissions on the primary channel; and transmitting and receiving data on the secondary channel when an unacceptable level of interference is detected on the primary channel. In an alternate embodiment, data is preferably transmitted on a primary and a secondary channel during separate periods of a transmission interval. If an unacceptable level of interference is detected on either the primary or secondary channels, then the other channel is used for data transmission during one of the periods while another one of the periods is used to identify a new channel substantially free from interference to replace the bad channel.

Abstract: Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.

Abstract: A wireless tracking device including a positioning system for determining a location of the device and a processor connected to the positioning system. The wireless tracking device further including a wireless radio connected to the processor for transmitting the location of the device across a wireless area network. A vehicle monitoring system including a sensor, a microcontroller configured to receive a sensor input from the sensor and determine a vehicle condition data, and a wireless transmitter in communication with the microcontroller. The wireless transmitter is configured to transmit the vehicle condition data to a remote data network access point. A method of monitoring a vehicle including determining a status of the vehicle, locating an available wireless data network access point, and transmitting the status of the vehicle though the access point.

Abstract: In one embodiment, a method of fabricating a transistor for a memory cell includes the steps of performing a counter doping implant before or after a source/drain implant. The counter doping implant may comprise one or more implant steps that move a metallurgical junction formed by a well and a highly doped region closer to a surface of the substrate. The counter doping implant may also increase the concentration of the dopant of the well. The counter doping implant and the source/drain implant may be performed using the same mask. Transistors fabricated using embodiments of the present invention may be employed in memory cells to reduce soft error rates.

Abstract: An integrated circuit device (200) can include a main portion (204) and a built-in self-test (BIST) portion (204) having outputs coupled to physical input structures (e.g., bond pads) (206) of the integrated circuit device (200). A BIST portion (202) can test timing critical parameters that take into account the effect of input structures (206). A BIST portion (202) can apply BIST test signals with a pipeline structure that can emulate timing parameters, such as a set-up time (Ts) and a clock-to-output time (Tco).

Abstract: The present invention discloses an amplifying circuit, comprising an amplifying element with at least an input terminal and an output terminal. A signal input node is provided, the signal levels of which at least two moments in time are to be amplified by the amplifying element. At least two connecting lines are provided between the signal input node and the amplifying element, for transferring a signal from the signal input node to the input terminal of the amplifying element. A memory element is located on at least one of the connecting lines, for storing a signal level of the signal input node at a moment in time, and a switching element is disposed on each connecting line, between the memory element and the input terminal of the amplifying element if a memory element is provided on the connecting line, for consecutively connecting signal levels of the signal input node at different moments in time to the same amplifying element.

Abstract: A phase locked loop (PLL) can include a test loop filter (100) that generates a control voltage (VCTRL) for input to a voltage controlled oscillator (VCO). In a test mode, a control voltage can be varied and resulting output frequencies recorded, from which an open loop bandwidth can be determined. A control voltage can be varied by enabling a switch element (104-1) that can provide a current path through load resistance (RL) of test loop filter (100). Current provided to the test loop filter can be varied according to test signals to provide a variable control voltage (VCTRL).

Abstract: In one embodiment, an integrated circuit device includes a power on reset (POR) circuit and a stochastic reset circuit configured to control enabling and disabling of the POR circuit. The stochastic reset circuit may have a value from among many possible values. The POR circuit may be enabled during a power up sequence of the device when the value of the stochastic reset during the power up is not a value designated to allow disabling of the POR circuit. The stochastic reset circuit may be configured such that the probability of the POR circuit being disabled during the power up is extremely low. After the power up sequence, the stochastic reset circuit may be controlled to allow disabling of the POR circuit to conserve power.

Abstract: A method for fabricating a magnetic random access memory circuit (MRAM) and a MRAM circuit resulting therefrom are provided. The method includes depositing a first conductive layer upon and in contact with a plurality of magnetic cell junctions and selectively removing portions of the first conductive layer arranged above the plurality of magnetic cell junctions. In addition, the method includes depositing a second conductive layer above remaining portions of the first conductive layer and the plurality of magnetic cell junctions. The resulting circuit may include a field-inducing line having thickness and/or width variations relative to underlying magnetic cell junctions.

Abstract: A system and method for bi-directional communication between a system controller and a fan controller: The system operates in two modes and there are two communication paths between the system controller and the fan controller. The first communication path provides a PWM signal the frequency of which indicates the mode in which the system is operating. During the first mode, the duty cycle of the PWM signal on the first signal path indicates the desired fan speed. In the first mode, the second communication path carries a conventional tachometer signal. In the second mode the second communication path operates as a bi-directional communications signal path between said system controller and said fan controller.

Abstract: A shunt type voltage regulator circuit (300) can include a load supply circuit (306) and feedback circuit (308-0) that provide impedance modulated according to a first feedback circuit (308), thus limiting power consumption at higher power supply ranges. In addition, a faster regulation response can be provided by a current conveyor circuit (312?) that can force the voltage at a regulated load node (304) to match that at a replication node (316).

Abstract: A system and method for dynamically lock the sample rate of an analog to digital (ADC) converter to an input frequency. Specifically, a system for measuring power is disclosed. The system includes an ADC converter, a measuring module, an ADC cycle counter, and a calculation block coupled together. The ADC converter samples an analog input line signal. The measuring module measures a predetermined number of line cycles of the analog input line signal. The ADC cycle counter measures an actual sample count of the analog input line signal by the ADC converter over the predetermined number of line cycles. The calculation block determines an error rate between the actual sample count and an ideal sample count that is based on a predetermined over sample rate.