Abstract: A method of generating an application programming interface (API) for an electronic circuit. A graphical user interface is displayed through which a user can initiate generation of the API. A component is selected from a plurality of components for placement in said electronic circuit. The component represents an implementable function in the electronic circuit. The component is configured using the graphical user interface. The data pertaining to the selected component and the configuration of the component is stored. The graphical user interface is utilized to access the stored data. The interface is initiated to invoke a processing of said data which causes a generation of the application programming interface. The application interface is for controlling the function of the component in said electronic circuit.

Abstract: A method for generating a channel stream. The method generally comprises the steps of (A) transforming a plurality of data streams, wherein every data stream entering the channel stream experiences a unique transformation and (B) serializing the data streams as transformed into the channel stream.

Abstract: A disclosed circuit includes circuitry for coupling to a volatile memory, circuitry for coupling to a nonvolatile NAND flash memory, and circuitry that: (i) receives a volatile memory request from a processor and satisfies the volatile memory request by accessing the volatile memory, and (ii) receives a nonvolatile NOR flash memory read request from the processor and satisfies the NOR read request by accessing both the NAND flash memory and the volatile memory. The circuit may also include circuitry that receives a volatile memory request from another processor and satisfies the volatile memory request from the other processor by accessing the volatile memory, and circuitry that receives a NAND flash memory read request from the other processor and satisfies the NAND read request by accessing the NAND flash memory. Multiprocessor systems including the circuit are described, as is a method for satisfying a NOR flash memory read request.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to synchronize at least one transport overhead byte with a pulse on an external pin. The second circuit may be configured to synchronize the transport overhead byte to the overhead processor. The overhead processor may be synchronized with (i) an overhead generator and (ii) an overhead extractor.

Abstract: An analog-to-digital converter (ADC) architecture to implement a non-linear flash ADC. The apparatus includes a non-linear resistor, a non-linear comparator, and an inverse non-linear encoder. The non-linear resistor has an input and a plurality of non-linear voltage outputs. The non-linear comparator ladder is coupled to the plurality of non-linear voltage outputs of the non-linear resistor. The non-linear comparator ladder includes a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs. The inverse non-linear encoder is coupled to the non-linear comparator ladder. The inverse non-linear encoder generates a digital output code based on the input signal and the plurality of non-linear voltage signals.

Abstract: A frequency synthesis/multiplication circuit and method for multiplying the frequency of a reference signal. In one embodiment, multiple versions of the reference signal are generated having different phases relative to one another, and these multiple versions are combined to form an output signal having a frequency that is a multiple of the frequency of the reference signal.

Abstract: A wireless Universal Serial Bus (USB) device enumerates one or more real or virtual hubs that support transmission of USB data over a wireless network. The number of virtual hubs presented to a USB host can be varied dynamically according to monitored characteristics of the wireless network, such as the propagation delay, Bit Error Rate, or USB configuration of the peripheral device. Another aspect of the wireless system varies a USB transmission rate according to the amount of bandwidth available on the wireless network.

Abstract: In one embodiment, a probe card for testing dice on a wafer includes a substrate, a number of cantilevers formed on a surface thereof, and a number of probes extending from unsupported ends of the cantilevers. The unsupported ends of the cantilevers project over cavities on the surface of the substrate. The probes have tips to contact pads on the dice under test. The probe card may include a compressive layer above the surface of the substrate with a number of holes through which the probes extend.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.

Abstract: In one arrangement, a semiconductor memory device can include a sense amplifier circuit (300) having drive high transistors (P30/P31), drive low transistors (N31/N32) and equalization transistors (N33-N35). Such transistors can have a body bias (VbiasN, VbiasP) that varies according to the operation conditions of the semiconductor memory device. Such variations can include any of: manufacturing process variations, operating temperature, or operating voltage.

Abstract: Disclosed is a circuit, comprising an input spread spectrum enable signal, a crystal oscillator, a first, second and third sampling flip-flop clocked by the crystal oscillator, configured to sample the input spread spectrum enable signal, and a plurality of control output signals derived from or provided directly from the sampling flip-flops. A method of operating the circuit is further described.

Abstract: An address transition detector (ATD) system is provided with an integrator, a feedback circuit and an output circuit. The integrator has an enhanced architecture that ensures a fast output signal switching, low power consumption during the integration time, fast output transition at the end of the integration time and compensates the delay variations over process, voltage and temperature (PVT) fluctuations. The ATD system can be used in any asynchronous memory. In addition, the ATD integrator can be employed as a standalone circuit for use whenever a signal transition is to be delayed.

Abstract: A system and method for bi-directional communication between a system controller and a fan controller: The system operates in two modes and there are two communication paths between the system controller and the fan controller. The first communication path provides a PWM signal the frequency of which indicates the mode in which the system is operating. During the first mode, the duty cycle of the PWM signal on the first signal path indicates the desired fan speed. In the first mode, the second communication path carries a conventional tachometer signal. In the second mode the second communication path operates as a bi-directional communications signal path between said system controller and said fan controller.

Abstract: According to one embodiment, a phase-locked loop (PLL) device includes test circuitry for entering/exiting a test mode upon receiving a particular pulse train at a reference clock input of the PLL. In addition, exemplary methods are provided herein for entering a test mode and detecting loop filter leakage within the PLL. The methods described herein are performed without the use of a dedicated test pin.

Abstract: A test circuit, system, and method are provided herein for testing one or more circuit components arranged upon a monolithic substrate. According to one embodiment, the system may include a test circuit and one or more circuit components, all of which are arranged upon the same monolithic substrate. In general, the test circuit may be configured for: (i) receiving an input signal at an input frequency, (ii) generating a test signal by modulating a phase of the input signal in accordance with a periodic signal, and (iii) supplying either the input signal or the test signal to the one or more integrated circuits, based on a control signal supplied to the test circuit. More specifically, the test circuit may be used to determine the jitter and/or duty cycle distortion (DCD) tolerance of any system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system.

Abstract: In one embodiment, a selective tungsten deposition process includes the steps of pre-flowing silane into a deposition chamber, pumping down the chamber, and then selectively depositing tungsten on a silicon surface. The silane pre-flow helps minimize silicon consumption, while the pump down helps prevent loss of tungsten selectivity to silicon.

Abstract: In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.

Abstract: In one embodiment, the invention is an apparatus for testing differential delay correction of network elements using virtual concatenation. The apparatus includes a first PRBS (pseudo-random bit stream) generator dedicated to a first tributary. The apparatus also includes an interface between the first PRBS generator and a tester. The apparatus further includes an interface between the first PRBS generator and a device under test. The apparatus may further include a second PRBS dedicated to a second tributary. The apparatus may also include a control logic block to control the first PRBS generator and the second PRBS generator, and coupled to the first PRBS generator and the second PRBS generator.

Abstract: A method of forming a phosphosilicate glass, includes flowing a pre-deposition gas comprising an inert gas into a deposition chamber containing a substrate, where the temperature of the substrate is at a pre-deposition temperature of at least 400° C; continuously increasing the temperature of gas in the chamber to a deposition temperature and simultaneously continuously increasing a flow rate of phosphine and silane until a phosphine:silane deposition ratio is achieved; and depositing the phosphosilicate glass on the substrate at the deposition temperature and at the phosphine:silane deposition ratio.

Abstract: Circuits for regulating a voltage or current to a load(s).